TMP401

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SBOS371B – AUGUST 2006 – REVISED OCTOBER 2014

7.5 Programming

7.5.1 Bus Overview

The TMP401 is SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer is called a

master, and the devices controlled by the master are slaves. The bus must be controlled by a master device that

generates the serial clock (SCL), controls the bus access, and generates the start and stop conditions.

To address a specific device, a start condition is initiated. A start condition is indicated by pulling the data line

(SDA) from a high to low logic level while SCL is high. All slaves on the bus shift in the slave address byte, with

the last bit indicating whether a read or write operation is intended. During the ninth clock pulse, the slave being

addressed responds to the master by generating an acknowledge and pulling SDA low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer SDA must remain stable while SCL is high, because any change in SDA while SCL is high is interpreted

as a control signal.

When all data are transferred, the master generates a stop condition. A stop condition is indicated by pulling

SDA from low to high while SCL is high.

7.5.2 Serial Interface

The TMP401 operates only as a slave device on either the two-wire bus or the SMBus. Connections to either bus

are made via the open-drain I/O lines, SDA and SCL. The SDA and SCL pins feature integrated spike-

suppression filters and Schmitt triggers to minimize the effects of input spikes and bus noise. The TMP401

supports the transmission protocol for fast (1 kHz to 400 kHz) and high-speed (1 kHz to 2.5 MHz) modes. All

data bytes are transmitted MSB first.

7.5.3 Serial Bus Address

To communicate with the TMP401, the master must first address slave devices via a slave address byte. The

slave address byte consists of seven address bits, and a direction bit indicating the intent of executing a read or

write operation. The address of the TMP401 is 4Ch (1001100b).

7.5.4 Read and Write Operations

Accessing a particular register on the TMP401 is accomplished by writing the appropriate value to the pointer

register. The value for the pointer register is the first byte transferred after the slave address byte with the R/W

bit low. Every write operation to the TMP401 requires a value for the pointer register (see Figure 13).

When reading from the TMP401, the last value stored in the pointer register by a write operation is used to

determine which register is read by a read operation. To change the register pointer for a read operation, a new

value must be written to the pointer register. This transaction is accomplished by issuing a slave address byte

with the R/W bit low, followed by the pointer register byte. No additional data are required. The master can then

generate a start condition and send the slave address byte with the R/W bit high to initiate the read command.

See Figure 14 for details of this sequence. If repeated reads from the same register are desired, continually

sending the pointer register bytes is not necessary, because the TMP401 retains the pointer register value until

changed by the next write operation. Note that register bytes are sent MSB first, followed by the LSB.

7.5.5 Timeout Function

When bit 7 of the consecutive alert register is set high, the TMP401 timeout function is enabled. The TMP401

resets the serial interface if either SCL or SDA are held low for 30 ms (typ) between a start and stop condition. If

the TMP401 is holding the bus low, the device releases the bus and waits for a start condition. To avoid

activating the timeout function, a communication speed of at least 1 kHz must be maintained for the SCL

operating frequency. The default state of the timeout function is enabled (bit 7 = high).

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