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TMP401 Datasheet(PDF) 7 Page - Texas Instruments |
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TMP401 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 41 page ![]() TMP401 www.ti.com SBOS371B – AUGUST 2006 – REVISED OCTOBER 2014 6.6 Timing Requirements See the Timing Diagrams section for timing diagrams. FAST MODE HIGH-SPEED MODE PARAMETER MIN MAX MIN MAX UNIT f(SCL) SCL operating frequency 0.001 0.4 0.001 2.5 MHz t(BUF) Bus free time between stop and start condition 600 160 ns Hold time after repeated start condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. t(SUSTA) Repeated start condition setup time 600 160 ns t(SUSTO) Stop condition setup time 600 160 ns t(HDDAT) Data hold time 100 80 ns t(SUDAT) Data setup time 100 60 ns t(LOW) SCL clock low period 1300 260 ns t(HIGH) SCL clock high period 600 60 ns Clock rise and fall time 300 40 ns tF Data fall time 300 120 ns 300 ns tR Data rise time for SCL ≤ 100 kHz 1000 ns Copyright © 2006–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TMP401 |
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