LM43602 datasheet(3/44 Pages) TI2

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VIN

PGND

CBOOT

VCC

BIAS

SYNC

PGOOD

SS/TRK

AGND

PGND

VIN

PAD

LM43602-Q1

www.ti.com

SNVSA83C – APRIL 2015 – REVISED OCTOBER 2017

Product Folder Links: LM43602-Q1

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5 Pin Configuration and Functions

PWP Package

16-Pin HTSSOP

Top View

(1)

P = Power, G = Ground, A = Analog

Pin Functions

TYPE(1)

DESCRIPTION

NAME

NUMBER

1,2

Switching output of the regulator. Internally connected to both power MOSFETs. Connect to

power inductor.

CBOOT

Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF capacitor

from CBOOT to SW.

VCC

Internal bias supply output for bypassing. Connect bypass capacitor from this pin to AGND.

Do not connect external loading to this pin. Never short this pin to ground during operation.

BIAS

Optional internal LDO supply input. To improve efficiency, it is recommended to tie to VOUT

when 3.3 V

≤ VOUT ≤ 28 V, or tie to an external 3.3 V or 5 V rail if available. When used, place

a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when not in use. BIAS

pin voltage should not exceed VIN.

SYNC

Clock input to synchronize switching action to an external clock. Use proper high speed

termination to prevent ringing. Connect to ground if not used.

Connect a resistor RT from this pin to AGND to program switching frequency. Leave floating

for 500 kHz default switching frequency.

PGOOD

Open drain output for power-good flag. Use a 10 kΩ to 100 kΩ pullup resistor to logic rail or

other DC voltage no higher than 12 V.

Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do not

short this pin to ground during operation.

AGND

Analog ground pin. Ground reference for internal references and logic. Connect to system

ground.

SS/TRK

Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a capacitor to

extend soft start time. Connect to external voltage ramp for tracking.

Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to VIN, or

to VIN through resistor divider,or to an external voltage or logic source. Do not float.

VIN

13,14

Supply input pins to internal LDO and high side power FET. Connect to power supply and

bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND must be as

short as possible.

PGND

15,16

Power ground pins, connected internally to the low side power FET. Connect to system

ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as possible.

PAD

—

Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation path

of the die. Must be used for heat sinking to ground plane on PCB.

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