LM43602 datasheet(34/44 Pages) TI2

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LM43602-Q1

SNVSA83C – APRIL 2015 – REVISED OCTOBER 2017

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Layout Guidelines (continued)

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components of

the pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the VIN and PGND pins is the

key to EMI reduction.

The SW pin connecting to the inductor must be as short as possible, and just wide enough to carry the load

current without excessive heating. Use short, thick traces or copper pours (shapes) high current conduction path

to minimize parasitic resistance. Place the output capacitors close to the VOUT end of the inductor, closely

grounded to PGND pin and exposed PAD.

Place the bypass capacitors on VCC and BIAS pins as close as possible to the pins, respectively, and closely

ground to PGND and the exposed PAD.

10.1.2 Ground Plane and Thermal Considerations

TI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding for

sensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect the

AGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins are

connected to the source of the internal LS switch. They must be connected directly to the grounds of the input

and output capacitors. The PGND net contains noise at switching frequency and may bounce due to load

variations. PGND trace, as well as PVIN and SW traces, must be constrained to one side of the ground plane.

The other side of the ground plane contains much less noise and should be used for sensitive routes.

TI recommends providing adequate device heat sinking by utilizing the PAD of the device as the primary thermal

path. Use a recommended 4 by 3 array of 10-mil thermal vias to connect the PAD to the system ground plane

heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible for system

ground plane on the top and bottom layers for the best heat dissipation. Use a four-layer board with the copper

thickness for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enough

copper thickness provides low current conduction impedance, proper shielding and lower thermal resistance.

The thermal characteristics of the LM43602-Q1 are specified using the parameter RθJA, which characterize the

junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJA is

dependant on many variables, it still can be used to approximate the operating junction temperature of the

device. To obtain an estimate of the device junction temperature, one may use Equation 27:

TJ = PD × RθJA + TA

where

•

TJ = junction temperature in °C

•

PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR

•

DCR = inductor DC parasitic resistance in Ω

•

RθJA = junction-to-ambient thermal resistance of the device in °C/W

•

TA = ambient temperature in °C

(27)

The maximum operating junction temperature of the LM43602-Q1 is 125°C. RθJA is highly related to PCB size

and layout, as well as enviromental factors such as heat sinking and air flow. Figure 64 shows measured results

of RθJA with different copper area on a 2-layer board and a 4-layer board.

LM43602 Datasheet(PDF) 34 Page - Texas Instruments

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