20.0

25.0

30.0

35.0

40.0

45.0

50.0

20mm x 20mm

30mm x 30mm

40mm x 40mm

50mm x 50mm

Copper Area

1W @ 0fpm - 2 layer

2W @ 0fpm - 2 layer

1W @ 0fpm - 4 layer

2W @ 0fpm - 4 layer

C007

35

LM43602-Q1

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SNVSA83C – APRIL 2015 – REVISED OCTOBER 2017

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Layout Guidelines (continued)

Figure 64. RθJA vs Copper Area

2 oz Copper on Outer Layers and 1 oz Copper on Inner Layers

10.1.3 Feedback Resistors

To reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider and

CFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a high

impedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces the

trace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the trace

from VOUT to the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects for

voltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load to

the feedback resistor divider should be routed away from the SW node path and the inductor to avoid

contaminating the feedback signal with switch noise, while also minimizing the trace length. This is most

important when high value resistors are used to set the output voltage. This provides further shielding for the

voltage feedback path from EMI noises.