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LM43602-Q1

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SNVSA83C – APRIL 2015 – REVISED OCTOBER 2017

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Copyright © 2015–2017, Texas Instruments Incorporated

(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

(2)

The package thermal impedance is calculated in accordance with JESD 51-7;

(3)

Thermal resistances were simulated on a 4 layer, JEDEC board.

(4)

See Figure 64 for RθJA vs Copper Area curve.

6.4 Thermal Information

THERMAL METRIC(1)(2)(3)

LM43602-Q1

UNIT

PWP (HTSSOP )

16 PINS

RθJA

Junction-to-ambient thermal resistance

38.9(4)

°C/W

RθJC(top)

Junction-to-case (top) thermal resistance

24.3

°C/W

RθJB

Junction-to-board thermal resistance

19.9

°C/W

ψJT

Junction-to-top characterization parameter

0.7

°C/W

ψJB

Junction-to-board characterization parameter

19.7

°C/W

RθJC(bot)

Junction-to-case (bottom) thermal resistance

1.7

°C/W

6.5 Electrical Characteristics

Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.

Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most

likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following

conditions apply: VIN = 12 V, VOUT = 3.3 V, FS = 500 kHz.

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY VOLTAGE (VIN PIN)

VIN-MIN-ST

Minimum input voltage for startup

3.8

V

ISHDN

Shutdown quiescent current

VEN = 0 V

1.2

3.1

µA

IQ-NONSW

Operating quiescent current (non-

switching) from VIN

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external

5

10

µA

IBIAS-NONSW

Operating quiescent current (non-

switching) from external VBIAS

VEN = 3.3 V

VFB = 1.5 V

VBIAS = 3.4 V external

85

130

µA

IQ-SW

Operating quiescent current (switching)

VEN = 3.3 V

IOUT = 0 A

RT = open

VBIAS = VOUT = 3.3 V

RFBT = 1 Meg

27

µA

ENABLE (EN PIN)

VEN-VCC-H

Voltage level to enable the internal LDO

output VCC

VENABLE high level

1.2

V

VEN-VCC-L

Voltage level to disable the internal LDO

output VCC

VENABLE low level

0.525

V

VEN-VOUT-H

Precision enable level for switching and

regulator output: VOUT

VENABLE high level

2

2.2

2.42

V

VEN-VOUT-HYS

Hysteresis voltage between VOUT

precision enable and disable thresholds

VENABLE hysteresis

–290

mV

ILKG-EN

Enable input leakage current

VEN = 3.3 V

0.85

1.75

µA

INTERNAL LDO (VCC and BIAS PINS)

VCC

Internal LDO output voltage VCC

VIN ≥ 3.8 V

3.28

V

VCC-UVLO

Undervoltage lock out (UVLO)

thresholds for VCC

VCC rising threshold

3.1

V

Hysteresis voltage between rising and

falling thresholds

–520

mV

VBIAS-ON

Internal LDO input change over

threshold to BIAS

VBIAS rising threshold

2.94

3.18

V

Hysteresis voltage between rising and

falling thresholds

–75

mV