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GL3522 Datasheet(PDF) 13 Page - GENESYS LOGIC

Part # GL3522
Description  USB 3.0 Hub Controller
PDF  32 Pages
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Manufacturer  GENESYS [GENESYS LOGIC]
Direct Link  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL3522 Datasheet(HTML) 13 Page - GENESYS LOGIC

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GL3522-22 Datasheet
© 2014 Genesys Logic, Inc. - All rights reserved.
Page 13
GLI Confidential
Clock and Reset Interface
Pin Name
QFN 76 / LGA 76
Type
Description
X1
4
I
Crystal / OSC clock input
X2
5
O
Crystal clock output.
RESETJ
69
I (pd)
Active low. External reset input, default pull high 10KΩ.
When RESET# = low, whole chip is reset to the initial state.
SPI Interface
Pin Name
QFN 76 / LGA 76
Type
Description
P_SPI_CK
51
B
For SPI data clock
P_SPI_CZ
52
B
For SPI data chip enable
P_SPI_DO
66
B
For SPI data Input
P_SPI_DI
67
B
For SPI data Output
Power/Ground Interface
Pin Name
QFN 76 / LGA 76
Type
Description
VP12
13,19,27,
35,43
P
Analog 1.2V power input for Analog circuit
DVDD12
46,61
P
1.2V digital power input for digital circuits
DVDD
57
P
3.3V digital power input for digital circuits
AVDD
58,59
P
Analog 3.3V power input
GND
10,16,24,
32,40
P
Digital/Analog ground
VBUS
56
I
VBUS valid input
V33
71
P
5V-to-3.3V regulator Vout & 3.3 input
V5
72,76
P
5V Power input. It should be NC if using external regulator
Miscellaneous Interface
Pin Name
QFN 76 / LGA 76
Type
Description
RTERM
3
A
A 680ohm resister must be connected between RTERM and Ground
TEST
62
B (pd)
TEST: 0: Normal operation.
1: Chip will be put in test mode.



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