GL3522-22 Datasheet

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Page 16

GLI Confidential

4.2 General Description

4.2.1 USB 2.0 USPORT Transceiver

USB 2.0 USPORT (upstream port) transceiver is the analog circuit that supports both full-speed and

high-speed electrical characteristics defined in Chapter 7 of USB specification revision 2.0. USPORT

transceiver will operate in full-speed electrical signaling when GL3522-22 is plugged into a 1.1 host/hub.

USPORT transceiver will operate in high-speed electrical signaling when GL3522-22 is plugged into a 2.0

host/hub.

4.2.2 USB 3.0 USPORT Transceiver

USB 3.0 USPORT (upstream port) transceiver is the analog circuit that has elastic buffer and supports

receiver detection, data serialization and de-serialization. Besides, it has PIPE interface with SuperSpeed

Link Layer

4.2.3 PLL (Phase Lock Loop)

PLL generates the clock sources for the whole chip. The generated clocks are proven quite accurate that help

in generating high speed signal without jitter.

4.2.4 Regulator

GL3522-22 build in internal regulators convert 5V input to 3.3V/1.2V output.

4.2.5 SPI Engine

SPI engine is to move code from external flash to the internal RAM.

4.2.6 RAM/ROM/CPU

The micro-processor unit of GL3522-22 is an 8-bit RISC processor with 16K-byte ROM and 256-bytes

RAM. It operates at 12MIPS of 12 MHz clock( maximum) to decode the USB command issued from host

and then prepares the data to respond to the host.

4.2.7 UTMI (USB 2.0 Transceiver Microcell Interface)

UTMI handles the low level USB protocol and signaling. It’s designed based on the Intel’s UTMI

specification 1.01. The major functions of UTMI logic are to handle the data and clock recovery, NRZI

encoding/decoding, Bit stuffing /de-stuffing, supporting USB 2.0 test modes, and serial/parallel conversion.

4.2.8 SIE (Serial Interface Engine)

SIE handles the USB protocol defined in Chapter 8 of USB specification revision 2.0. It co-works with μ C

to play the role of the hub kernel. The main functions of SIE include the state machine of USB protocol flow,

CRC check, PID error check, and timeout check. Unlike USB 1.1, bit stuffing/de-stuffing is implemented in

UTMI, not in SIE.

4.2.9 Control/Status Register

Control/Status register is the interface register between hardware and firmware. This register contains the

information necessary to control endpoint0 and endpoint1 pipelines. Through the firmware based

architecture, GL3522-22 possesses higher flexibility to control the USB protocol easily and correctly.

4.2.10 Power Management Engine

The power management of GL3522-22 is compliant with USB 3.0 specification. When operating in

SuperSpeed mode, GL3522-22 supports U0, U1, U2, and U3 power states. U0 is the functional state. U1 and

U2 are lower power states compared to U0. U1 is a low power state with fast exit to U0; U2 is a low power

state which saves more power than U1 with slower exit to U0. U3 is suspend state, which is the most

power-saving state, with tens of milliseconds exit to U0. Unlike USB 2.0, SuperSpeed packet traffic is