GL3522-22 Datasheet

© 2014 Genesys Logic, Inc. - All rights reserved.

Page 19

GLI Confidential

4.3 Configuration and I/O Settings

4.3.1 RESET Setting

GL3522-22’s power on reset can either be triggered by external reset or internal power good reset circuit.

The external reset pin, RESETJ, is connected to upstream port Vbus (5V) to sense the USB plug / unplug or

5V voltage drop. The reset trigger voltage can be set by adjusting the value of resistor R1 and R2 (Suggested

value refers to schematics) GL3522-22’s internal reset is designed to monitor silicon’s internal core power

(1.2V) and initiate reset when unstable power event occurs. The power on sequence will start after the power

good voltage has been met, and the reset will be released after approximately 40 μS after power good.

GL3522-22’s reset circuit as depicted in the picture.

Global

Reset#

Int. 3.3V power-good

detection circuit input

(USB PHY reset)

INT

EXT

Ext. VBUS power-good

detection circuit input

(Pin"RESET#")

VBUS

(External 5V)

PCB

Silicon

R1

R2

Pin

“VBUS”

Figure 4.4 - Power on Reset Diagram

To fully control the reset process of GL3522-22, we suggest the reset time applied in the external reset circuit

should longer than that of the internal reset circuit. Timing of POR is illustrated as below figure.

Internal reset

External reset

Power good voltage, 2.5V~2.8V (3.3V)

0.861V (1.2V)

VCC(3.3V)

(1.2V)

≒ 40 μs

Figure 4.5 - Power on Sequence of GL3522-22