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INA302 Datasheet(PDF) 31 Page - Texas Instruments |
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INA302 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 42 page ![]() 31 INA302, INA303 www.ti.com SBOS775C – SEPTEMBER 2016 – REVISED MARCH 2019 Product Folder Links: INA302 INA303 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated 9 Power Supply Recommendations The device input circuitry accurately measures signals on common-mode voltages beyond the power-supply voltage, VS. For example, the voltage applied to the VS power-supply pin can be 5 V, whereas the load power- supply voltage being monitored (VCM) can be as high as 36 V. At power-up, for applications where the common- mode voltage (VCM) slew rate is greater than 6 V/μs with a final common-mode voltage greater than 20 V, the VS supply is recommended to be present before VCM. If the use case requires VCM to be present before VS with VCM under these same slewing conditions, then a 331-Ω resistor must be added between the VS supply and the VS pin bypass capacitor. Power-supply bypass capacitors are required for stability, and must be placed as close as possible to the supply and ground pins of the device. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy or high-impedance power supplies may require additional decoupling capacitors to reject power-supply noise. During slow power-up events, current flow through the sense resistor or voltage applied to the REF pin can result in the output voltage momentarily exceeding the voltage at the LIMITx pins, resulting in an erroneous indication of an out-of-range event on the ALERTx output. When powering the device with a slow ramping power rail where an input signal is already present, all alert indications should be disregarded until the supply voltage has reached the final value. 10 Layout 10.1 Layout Guidelines • Apply connections to the current-sense resistor, RSENSE, on the inside of the resistor pads to avoid additional voltage losses incurred by the high current traces to the resistor. Route the traces from the current-sense resistor symmetrically and side-by-side back to the input of the INA to minimize common-mode errors and noise pickup. • Place the power-supply bypass capacitor as closely as possible to the supply and ground pins. The recommended value of this bypass capacitor is 0.1 µF. Additional decoupling capacitance can be added to compensate for noisy or high-impedance power supplies. • Make the connection of RLIMIT to the ground pin as direct as possible to limit additional capacitance on this node. Routing this connection must be limited to the same plane if possible to avoid vias to internal planes. If the routing can not be made on the same plane and must pass through vias, make sure that a path is routed from RLIMIT back to the ground pin, and that RLIMIT is not simply connected directly to a ground plane. • Routing to the delay capacitor must be short and direct. Keep the routing trace from the DELAY pin to the delay capacitor away from the ALERT2 trace (or any other noisy signals) to minimize any coupling effects. If no delay capacitor is used do not have any connection to the DELAY pin. Long trace lengths on the DELAY pin can cause noise to couple to the device, resulting in false trips. • Pull up the open-drain output pins to the supply voltage rail; a 10-kΩ pullup resistor is recommended. |
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