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XC2000 Datasheet(PDF) 77 Page - Infineon Technologies AG

Part # XC2000
Description  16/32-Bit Single-Chip Microcontroller with 32-Bit Performance
PDF  112 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

XC2000 Datasheet(HTML) 77 Page - Infineon Technologies AG

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XC2230L, XC2234L
XC2000 Family / Econo Line
Electrical Parameters
Data Sheet
73
V1.3, 2015-02
1) These parameter values cover the complete operating range. Under relaxed operating conditions
(temperature, supply voltage) typical values can be used for calculation.
2) The sum of DNL/INL/GAIN/OFF errors does not exceed the related TUE total unadjusted error.
3) If a reduced analog reference voltage between 1V and
V
DDPB / 2 is used, then there are additional decrease
in the ADC speed and accuracy.
4) If the analog reference voltage range is below
V
DDPB but still in the defined range of VDDPB / 2 and VDDPB is
used, then the ADC converter errors increase. If the reference voltage is reduced by the factor k (k<1), TUE,
DNL, INL, Gain and Offset errors increase also by the factor 1/k.
5) If the analog reference voltage is >
V
DDPB, then the ADC converter errors increase.
6) TUE is based on 12-bit conversion.
7) TUE is tested at
V
AREF = VDDPB = 5.0 V, VAGND = 0 V. It is verified by design for all other voltages within the
defined voltage range. The specified TUE is valid only if the absolute sum of input overload currents on analog
port pins (see
I
OV specification) does not exceed 10 mA, and if VAREF and VAGND remain stable during the
measurement time.
Table 22
ADC Parameters for Lower Voltage Range
Parameter
Symbol
Values
Unit
Note /
Test Condition
Min.
Typ.
Max.
Input resistance of the
selected analog channel
R
AIN CC
−
1.4
2.5
kOh
m
not subject to
production test
1)
Input resistance of the
reference input
R
AREF
CC
−
1.0
2.0
kOh
m
not subject to
production test
1)
Differential Non-Linearity
Error
2)3)4)5)
|
EA
DNL|
CC
−
2.5
5.5
LSB
Gain Error
2)3)4)5)
|
EA
GAIN|
CC
−
3.0
8.0
LSB
Integral Non-
Linearity
2)3)4)5)
|
EA
INL|
CC
−
2.5
7.5
LSB
Offset Error
2)3)4)5)
|
EA
OFF|
CC
−
2.0
5.5
LSB
Analog clock frequency
f
ADCI SR
2
−
16.7
MHz
Std. reference
input (
V
AREF)
2
−
12.1
MHz
Alt. reference
input (CH0)
Total Unadjusted Error
3)4)
|TUE|
CC
−
2.5
7.5
LSB
6)7)



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