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XC2000 Datasheet(PDF) 100 Page - Infineon Technologies AG |
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XC2000 Datasheet(HTML) 100 Page - Infineon Technologies AG |
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100 / 112 page ![]() XC2230L, XC2234L XC2000 Family / Econo Line Electrical Parameters Data Sheet 96 V1.3, 2015-02 Figure 21 USIC - SSC Master/Slave Mode Timing Note: This timing diagram shows a standard configuration where the slave select signal is low-active and the serial clock signal is not shifted and not inverted. t2 t1 USIC_SSC_TMGX.VSD Clock Output SCLKOUT Data Output DOUT t 3 t 3 t5 Data valid t4 First Transmit Edge Data Input DX0 Select Output SELOx Active Master Mode Timing Slave Mode Timing t11 t10 Clock Input DX1 Data Output DOUT t14 t14 Data valid Data Input DX0 Select Input DX2 Active t13 t12 Transmit Edge: with this clock edge , transmit data is shifted to transmit data output. Receive Edge: with this clock edge , receive data at receive data input is latched . Receive Edge Last Receive Edge Inactive Inactive Transmit Edge Inactive Inactive First Transmit Edge Receive Edge Transmit Edge Last Receive Edge t5 Data valid t4 Data valid t12 t13 Drawn for BRGH .SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal. |
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