AD6653 datasheet(37/80 Pages) AD

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AD6653

Rev. 0 | Page 37 of 80

Increment Gain (IG) and Decrement Gain (DG)

The increment gain and decrement gain indicators are intended

to be used together to provide information to enable external

gain control. The decrement gain indicator works in

conjunction with the coarse upper threshold bits, asserting

when the input magnitude is greater than the 3-bit value in the

coarse upper threshold register (Address 0x105). The increment

gain indicator, similarly, corresponds to the fine lower threshold

bits except that it is asserted only if the input magnitude is less

than the value programmed in the fine lower threshold register

after the dwell time elapses. The dwell time is set by the 16-bit

dwell time value located at Address 0x10A and Address 0x10B

and is set in units of ADC input clock cycles ranging from 1 to

65,535. The fine lower threshold register is a 13-bit register that

is compared with the magnitude at the output of the ADC. This

comparison is subject to the ADC clock latency but allows a

finer, more accurate comparison. The fine upper threshold

magnitude is defined by the following equation:

dBFS = 20 log(Threshold Magnitude/213)

The decrement gain output works from the ADC fast detect

output pins, providing a fast indication of potential overrange

conditions. The increment gain uses the comparison at the

output of the ADC, requiring the input magnitude to remain

below an accurate, programmable level for a predefined period

before signaling external circuitry to increase the gain.

The operation of the increment gain output and decrement gain

output is shown graphically in Figure 73.

UPPER THRESHOLD (COARSE OR FINE)

FINE LOWER THRESHOLD

F_LT

C_UT OR F_UT*

DWELL TIME

TIMER RESET BY

RISE ABOVE F_LT

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE F_LT

NOTE: OUTPUTS FOLLOW THE INSTANTANEOUS SIGNAL LEVEL AND NOT THE ENVELOPE BUT ARE GUARANTEED ACTIVE FOR A MINIMUM OF 2 ADC CLOCK CYCLES.

*C_UT AND F_UT DIFFER ONLY IN ACCURACY AND LATENCY.

DWELL TIME

Figure 73. Threshold Settings for C_UT, F_UT, F_LT, DG, and IG

AD6653 Datasheet(PDF) 37 Page - Analog Devices

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