AD6653 datasheet(24/80 Pages) AD

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AD6653

Rev. 0 | Page 24 of 80

THEORY OF OPERATION

The AD6653 has two analog input channels, two decimating

channels, and two digital output channels. The intermediate

frequency (IF) input signal passes through several stages before

appearing at the output port(s) as a filtered, decimated digital

signal.

The dual ADC design can be used for diversity reception of signals,

where the ADCs operate identically on the same carrier but from

two separate antennae. The ADCs can also be operated with inde-

pendent analog inputs. The user can sample any fS/2 frequency

segment from dc to 150 MHz, using appropriate low-pass or

band-pass filtering at the ADC inputs with little loss in ADC

performance. Operation to 450 MHz analog input is permitted

but occurs at the expense of increased ADC noise and distortion.

In nondiversity applications, the AD6653 can be used as a

baseband receiver, where one ADC is used for I input data,

and the other is used for Q input data.

Synchronization capability is provided to allow synchronized

timing between multiple channels or multiple devices. The

NCO phase can be set to produce a known offset relative to

another channel or device.

Programming and control of the AD6653 are accomplished

using a 3-bit SPI-compatible serial interface.

ADC ARCHITECTURE

AD6653 architecture consists of a front-end sample-and-hold

amplifier (SHA), followed by a pipelined switched-capacitor ADC.

The quantized outputs from each stage are combined into a final

12-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate on a new input

sample and the remaining stages to operate on the preceding

samples. Sampling occurs on the rising edge of the clock.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched-capacitor digital-

to-analog converter (DAC) and an interstage residue amplifier

(MDAC). The residue amplifier magnifies the difference between

the reconstructed DAC output and the flash input for the next

stage in the pipeline. One bit of redundancy is used in each stage to

facilitate digital correction of flash errors. The last stage simply

consists of a flash ADC.

The input stage of each channel contains a differential SHA that

can be ac- or dc-coupled in differential or single-ended modes.

The output staging block aligns the data, corrects errors, and

passes the data to the output buffers. The output buffers are

powered from a separate supply, allowing adjustment of the

output voltage swing. During power-down, the output buffers

go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6653 is a differential switched-

capacitor SHA that has been designed for optimum

performance while processing a differential input signal.

The clock signal alternatively switches the SHA between sample

mode and hold mode (see Figure 46). When the SHA is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within 1/2 of a clock cycle.

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the inputs

to provide dynamic charging currents. This passive network

creates a low-pass filter at the ADC input; therefore, the precise

values are dependent on the application.

In IF undersampling applications, any shunt capacitors should

be reduced. In combination with the driving source impedance,

the shunt capacitors limit input bandwidth. Refer to Application

Note AN-742, Frequency Domain Response of Switched-

Capacitor ADCs; Application Note AN-827, A Resonant Approach

to Interfacing Amplifiers to Switched-Capacitor ADCs; and the

Analog Dialogue article, “Transformer-Coupled Front-End for

Wideband A/D Converters,” for more information on this subject

(see www.analog.com). In general, the precise values are

dependent on the application.

VIN+

VIN–

CPIN, PAR

Figure 46. Switched-Capacitor SHA Input

For best dynamic performance, the source impedances driving

VIN+ and VIN− should be matched such that common-mode

settling errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC.

An internal differential reference buffer creates positive and

negative reference voltages that define the input span of the

ADC core. The output common mode of the reference buffer is

set to VCMREF (approximately 1.6 V).

Input Common Mode

The analog inputs of the AD6653 are not internally dc biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that VCM = 0.55 × AVDD is

recommended for optimum performance, but the device functions

over a wider range with reasonable performance (see Figure 45).

An on-board common-mode voltage reference is included in the

design and is available from the CML pin. Optimum performance

is achieved when the common-mode voltage of the analog input

is set by the CML pin voltage (typically 0.55 × AVDD).

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