AD6653 datasheet(51/80 Pages) AD

51 / 80 page

AD6653

Rev. 0 | Page 51 of 80

Bit 5—Peak Detector Output Enable

Bit 5 enables the 13-bit peak measurement as output on the

SPORT.

Bit 4—Threshold Crossing Output Enable

Bit 4 enables the 13-bit threshold measurement as output on the

SPORT.

Bits[3:2]—SPORT SMI SCLK Divide

The values of these bits set the SPORT SMI SCLK divide ratio from

the input clock. A value of 0x01 sets divide-by-2 (default), a value

of 0x10 sets divide-by-4, and a value of 0x11 sets divide-by-8.

Bit 1—SPORT SMI SCLK Sleep

Setting Bit 1 high causes the SMI SCLK to remain low when the

signal monitor block has no data to transfer.

Bit 0—Signal Monitor SPORT Output Enable

When set, Bit 0 enables the signal monitor SPORT output to

begin shifting out the result data from the signal monitor block.

Signal Monitor Control (Register 0x112)

Bit 7—Complex Power Calculation Mode Enable

This mode assumes I data is present on one channel and Q data

is present on the alternate channel. The result reported is the

complex power measured as

I +

Bits[6:4]—Reserved

Bit 3—Signal Monitor RMS/MS Select

Setting Bit 3 low selects rms power measurement mode. Setting

Bit 3 high selects ms power measurement mode.

Bits[2:1]—Signal Monitor Mode

Bit 2 and Bit 1 set the mode of the signal monitor for data

output to registers at Address 0x116 through Address 0x11B.

Setting these bits to 0x00 selects rms/ms magnitudde output,

setting these bits to 0x01 selects peak detector output, and

setting 0x10 or 0x11 selects threshold crossing output.

Bit 0—Signal Monitor Enable

Setting Bit 0 high enables the signal monitor block.

Signal Monitor Period (Register 0x113 to Register 0x115)

This 24-bit value sets the number of clock cycles over which the

signal monitor performs its operation. The minimum value for

this register is 128 cycles (programmed values less than 128

revert to 128).

Signal Monitor Result Channel A (Register 0x116 to

Channel A[19:16]

Channel A[15:8]

Channel A[7:0]

This 20-bit value contains the power value calculated by the

signal monitor block for Channel A. The content is dependent

on the settings in Register 0x112, Bits[2:1].

Signal Monitor Result Channel B (Register 0x119 to

Channel B[19:16]

Channel B[15:8]

Channel B[7:0]

This 20-bit value contains the power value calculated by the

signal monitor block for Channel B. The content is dependent

on the settings in Register 0x112, Bits[2:1].

NCO Control (Register 0x11D)

Bits[7:3]—Reserved

Bit 2—NCO32 Phase Dither Enable

When Bit 2 is set, phase dither in the NCO is enabled. When

Bit 2 is cleared, phase dither is disabled.

Bit 1—NCO32 Amplitude Dither Enable

When Bit 1 is set, amplitude dither in the NCO is enabled.

When Bit 1 is cleared, amplitude dither is disabled.

Bit 0—NCO32 Enable

When Bit 0 is set, this bit enables the 32-bit NCO operating at

the frequency programmed into the NCO frequency register.

When Bit 0 is cleared, the NCO is bypassed and shuts down for

power savings.

AD6653 Datasheet(PDF) 51 Page - Analog Devices

AD6653 Datasheet(HTML) 51 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

Datasheet Download

Link URL