AD6653 datasheet(40/80 Pages) AD

40 / 80 page

AD6653

Rev. 0 | Page 40 of 80

DC Correction Bandwidth

The dc correction circuit is a high-pass filter with a programmable

bandwidth (ranging between 0.15 Hz and 1.2 kHz at 125 MSPS).

The bandwidth is controlled by writing the 4-bit dc correction

control register located at Register 0x10C, Bits[5:2]. The following

equation can be used to compute the bandwidth value for the dc

correction circuit:

−

CLK

Corr

where:

k is the 4-bit value programmed in Bits[5:2] of Register 0x10C

(values between 0 and 13 are valid for k; programming 14 or 15

provides the same result as programming 13).

fCLK is the AD6653 ADC sample rate in hertz (Hz).

DC Correction Readback

The current dc correction value can be read back in Register 0x10D

and Register 0x10E for Channel A and Register 0x10F and

14-bit value that can span the entire input range of the ADC.

DC Correction Freeze

Setting Bit 6 of Register 0x10C freezes the dc correction at its

current state and continues to use the last updated value as the

dc correction value. Clearing this bit restarts dc correction and

adds the currently calculated value to the data.

DC Correction Enable Bits

Setting Bit 0 of Register 0x10C enables dc correction for use in

the signal monitor calculations. The calculated dc correction value

can be added to the output data signal path by setting Bit 1 of

SIGNAL MONITOR SPORT OUTPUT

The SPORT is a serial interface with three output pins: the SMI

SCLK (SPORT clock), SMI SDFS (SPORT frame sync), and SMI

SDO (SPORT data output). The SPORT is the master and drives

all three SPORT output pins on the chip.

SMI SCLK

The data and frame sync are driven on the positive edge of the

SMI SCLK. The SMI SCLK has three possible baud rates: 1/2, 1/4,

or 1/8 the ADC clock rate, based on the SPORT controls. The

SMI SCLK can also be gated off when not sending any data, based

on the SPORT SMI SCLK sleep bit. Using this bit to disable the

SMI SCLK when it is not needed can reduce any coupling errors

back into the signal path, if these prove to be a problem in the

system. Doing so, however, has the disadvantage of spreading

the frequency content of the clock. If desired the SMI SCLK can

be left running to ease frequency planning.

SMI SDFS

The SMI SDFS is the serial data frame sync, and it defines the

start of a frame. One SPORT frame includes data from both

datapaths. The data from Datapath A is sent just after the frame

sync, followed by data from Datapath B.

SMI SDO

The SMI SDO is the serial data output of the block. The data is

sent MSB first on the next positive edge after the SMI SDFS.

Each data output block includes one or more of rms magnitude,

peak level, and threshold crossing values from each datapath in

the stated order. If enabled, the data is sent, rms first, followed

by peak and threshold, as shown in Figure 77.

20 CYCLES

16 CYCLES

20 CYCLES

16 CYCLES

SMI SDFS

MSB

RMS/MS CH A

PK CH A

PK CH B

THR CH B

RMS/MS CH B

RMS/MS CH A

LSB

THR CH A

SMI SDO

SMI SCLK

GATED, BASED ON CONTROL

Figure 77. Signal Monitor SPORT Output Timing (RMS, Peak, and Threshold Enabled)

20 CYCLES

16 CYCLES

20 CYCLES

16 CYCLES

SMI SCLK

SMI SDFS

SMI SDO

MSB

RMS/MS CH A

LSB

THR CH A

RMS/MS CH B LSB

THR CH B

GATED, BASED ON CONTROL

Figure 78. Signal Monitor SPORT Output Timing (RMS and Threshold Enabled)

AD6653 Datasheet(PDF) 40 Page - Analog Devices

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