ADS1291IRSMT datasheet(29/83 Pages) TI2

29 / 83 page

ADS1291, ADS1292, ADS1292R

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SBAS502C – DECEMBER 2011 – REVISED APRIL 2020

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8.3.8 Data Format

The ADS1291, ADS1292, and ADS1292R outputs 24 bits of data per channel in binary twos complement format,

MSB first. The LSB has a weight of VREF / (2

23 – 1). A positive full-scale input produces an output code of

7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips at these codes

for signals exceeding full-scale. Table 10 summarizes ideal output codes for different input signals. All 24 bits

toggle when the analog input is at positive or negative full-scale.

(1)

Excludes effects of noise, linearity, offset, and gain error.

Table 10. Ideal Output Code versus Input Signal

INPUT SIGNAL, VIN

(AINP – AINN)

IDEAL OUTPUT CODE(1)

≥ VREF

7FFFFFh

+VREF / (2

23 – 1)

000001h

000000h

–VREF / (2

23 – 1)

FFFFFFh

≤ –VREF (2

23 / 223 – 1)

800000h

8.3.9 Multiple Device Configuration

The ADS1291, ADS1292, and ADS1292R are designed to provide configuration flexibility when multiple devices

are used in a system. The serial interface typically needs four signals: DIN, DOUT, SCLK, and CS. With one

additional chip select signal per device, multiple devices can be connected together. The number of signals

needed to interface n devices is 3 + n.

The right leg drive amplifiers can be daisy-chained as explained in the RLD Configuration with Multiple Devices

subsection of the ECG-Specific Functions section. To use the internal oscillator in a daisy-chain configuration,

one of the devices must be set as the master for the clock source with the internal oscillator enabled (CLKSEL

pin = 1) and the internal oscillator clock brought out of the device by setting the CLK_EN register bit to '1'. This

master device clock is used as the external clock source for the other devices.

ADS1291IRSMT Datasheet(PDF) 29 Page - Texas Instruments