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ADS1291IRSMT Datasheet(PDF) 49 Page - Texas Instruments

Part # ADS1291IRSMT
Description  ADS129x Low-Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements
PDF  83 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

ADS1291IRSMT Datasheet(HTML) 49 Page - Texas Instruments

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Hi-Z
START
DRDY
CS
SCLK
DIN
DOUT
RDATA Opcode
STATUS Word + Channel Data (up to 72 bits)
RDATA Opcode
49
ADS1291, ADS1292, ADS1292R
www.ti.com
SBAS502C – DECEMBER 2011 – REVISED APRIL 2020
Product Folder Links: ADS1291 ADS1292 ADS1292R
Submit Documentation Feedback
Copyright © 2011–2020, Texas Instruments Incorporated
8.5.2.8 SDATAC: Stop Read Data Continuous
This opcode cancels the Read Data Continuous mode. There is no restriction on the SCLK rate for this
command, but the following command must wait for 4 tCLK cycles.
8.5.2.9 RDATA: Read Data
Issue this command after DRDY goes low to read the conversion result (in Stop Read Data Continuous mode).
There is no restriction on the SCLK rate for this command, and there is no wait time needed for the subsequent
commands or data retrieval SCLKs. To retrieve data from the device after RDATA command is issued, make
sure either the START pin is high or the START command is issued. When reading data with the RDATA
command, the read operation can overlap the occurrence of the next DRDY without data corruption. Figure 53
shows the recommended way to use the RDATA command. RDATA is best suited for ECG- and EEG-type
systems where register setting must be read or changed often between conversion cycles.
Figure 53. RDATA Usage
8.5.2.10 Sending Multi-Byte Commands
The ADS1291, ADS1292, and ADS1292R serial interface decodes commands in bytes and requires 4 tCLK cycles
to decode and execute. Therefore, when sending multi-byte commands, a 4 tCLK period must separate the end of
one byte (or opcode) and the next.
Assume CLK is 512 kHz, then tSDECODE (4 tCLK) is 7.8125 µs. When SCLK is 16 MHz, one byte can be
transferred in 500 ns. This byte-transfer time does not meet the tSDECODE specification; therefore, a delay must be
inserted so the end of the second byte arrives 7.3125 µs later. If SCLK is 1 MHz, one byte is transferred in 8 µs.
Because this transfer time exceeds the tSDECODE specification, the processor can send subsequent bytes without
delay. In this later scenario, the serial port can be programmed to move from single-byte transfer per cycle to
multiple bytes.



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