ADS1291IRSMT datasheet(30/83 Pages) TI2

30 / 83 page

START

DRDY

SCLK

DIN

DOUT

ADS1292

(Device0)

START

DRDY

SCLK

DIN

DOUT

ADS1292R

(Device1)

START

(1)

CLK

INT

GPO0

GPO1

SCLK

MOSI

HostProcessor

MISO

CLK

START

Device

CLK

DRDY

START

CLK

START

Device

CLK

DRDY

START

CLK

DRDY

Note 1

Note 2

ADS1291, ADS1292, ADS1292R

SBAS502C – DECEMBER 2011 – REVISED APRIL 2020

www.ti.com

Product Folder Links: ADS1291 ADS1292 ADS1292R

Submit Documentation Feedback

When using multiple devices, the devices can be synchronized with the START signal. The delay from START to

the DRDY signal is fixed for a fixed data rate (see the START subsection of the SPI Interface section for more

details on the settling times). Figure 33 shows the behavior of two devices when synchronized with the START

signal.

(1)

Start pulse must be at least one tMOD cycle wide.

(2)

Settling time number uncertainty is one tMOD cycle.

Figure 33. Synchronizing Multiple Converters

8.3.9.1 Standard Mode

Figure 34 shows a configuration with two devices cascaded together. One of the devices is an ADS1292R (two-

channel with RESP) and the other is an ADS1292 (two-channel). Together, they create a system with four

channels. DOUT, SCLK, and DIN are shared. Each device has its own chip select. When a device is not selected

by the corresponding CS being driven to logic 1, the DOUT of this device is high-impedance. This structure

allows the other device to take control of the DOUT bus.

Figure 34. Multiple Device Configurations

ADS1291IRSMT Datasheet(PDF) 30 Page - Texas Instruments

ADS1291IRSMT Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

Datasheet Download

Link URL