BQ25882 datasheet(32/86 Pages) TI2

32 / 86 page

START (S)

STOP (P)

SDA

SCL

SDA

SCL

SDA

SCL

Data line stable;

Data valid

Change of

data allowed

BQ25883

SLUSDL3A – FEBRUARY 2019 – REVISED APRIL 2019

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Figure 24. Bit Transfers on the I2C bus

8.3.14.2 START and STOP Conditions

All transactions begin with a START (S) and are terminated with a STOP (P). A HIGH to LOW transition on the

SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the

SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START

condition, and free after the STOP condition.

Figure 25. START and STOP conditions on the I2C bus

8.3.14.3 Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is

unrestricted. Each byte has to be followed by an ACKNOWLEDGE (ACK) bit. Data is transferred with the Most

Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has

performed some other function, it can hold the SCL line low to force the master into a wait state (clock

stretching). Data transfer then continues when the slave is ready for another byte of data and releases the SCL

line.

BQ25882 Datasheet(PDF) 32 Page - Texas Instruments