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BQ25882 Datasheet(PDF) 11 Page - Texas Instruments |
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BQ25882 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 86 page  11 BQ25883 www.ti.com SLUSDL3A – FEBRUARY 2019 – REVISED APRIL 2019 Product Folder Links: BQ25883 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Electrical Characteristics (continued) VVBUS_UVLO_RISING< VVBUS < VVBUS_OV, TJ = -40°C to+125°C, and TJ = 25°C for typical values (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IBUS_ADC_RANGE ADC BUS current range 0 4 A IBUS_ADC_LSB ADC BUS current LSB 1 mA IBAT_ADC_RANGE ADC BAT current range 0 4 A IBAT_ADC_LSB ADC BAT current LSB 1 mA VBUS_ADC_RANGE ADC BUS voltage range 0 6.5 V VBUS_ADC_LSB ADC BUS voltage LSB 1 mV VSYS_ADC_RANGE ADC SYS voltage range 0 10 V VSYS_ADC_LSB ADC SYS voltage LSB 1 mV VBAT_ADC_RANGE ADC BAT voltage range 0 10 V VBAT_ADC_LSB ADC BAT voltage LSB 1 mV VTS_ADC_RANGE ADC TS voltage range 20 80 % VTS_ADC_LSB ADC TS voltage LSB 0.098 % VTDIE_ADC_RANGE ADC Die temperature range 0 150 °C VTDIE_ADC_LSB ADC Die temperature LSB 0.5 °C I2C INTERFACE (SCL, SDA) VIH Input high threshold level, SDA and SCL Pull-up rail 1.8 V 1.3 V VIL Input low threshold level Pull-up rail 1.8 V 0.4 V VOL Output low threshold level Sink current = 5 mA 0.4 V IBIAS High level leakage current Pull-up rail 1.8 V 1 uA LOGIC I/O PIN (/CE) VIH_CEZ Input high threshold level, /CE 1.3 V VIL_CEZ Input low threshold level, /CE 0.4 V IIN_BIAS_CEZ High level leakage current, /CE Pull-up rail 1.8 V 2.5 uA LOGIC O PIN (/INT, /PG, STAT) VOL Output low threshold level Sink current = 5 mA 0.4 V IOUT_BIAS High level leakage current Pull-up rail 1.8 V 1 µA 7.6 Timing Requirements PARAMETER TEST CONDITIONS MIN NOM MAX UNIT VBUS/BAT POWER UP tVBUS_OV VBUS OVP reaction time VBUS rising above VBUS_OV threshold to converter turn off 200 ns tPOORSRC Bad adapter detection duration 30 ms BATTERY CHARGER tTERM_DGL Deglitch time for charge termination Charge current falling below ITERM 250 ms tRECGH_DGL Deglitch time for recharge threshold BAT voltage falling below VRECHG = 100 mV 250 ms tBAT_OVP_DGL Deglitch time for battery over-voltage to disable charge 1 µs tTOP_OFF Typical Top-Off Timer Accuracy TOP_OFF_TIMER = 30 min 24 30 36 min tSAFETY Charge Safety Timer Accuracy CHG_TIMER = 12 hours 10.8 12 13.2 hr I2C INTERFACE fSCL SCL clock frequency 1000 kHZ tSU_STA Data set-up time 10 ns tHD_DAT Data hold time 0 70 ns trDA Rise time of SDA signal 10 80 ns |
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