L99H92 datasheet(51/77 Pages) STMICROELECTRONICS

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6.3

Status registers

Table 44. Status register DSR1 (0x01) MSB

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0 (R/C)

0 (R)

VDHOV

VDHUV

VSOVW

VDDOV

TSD

FSIN

NRDY

VDH

overvoltage

flag

VDH

undervoltage

flag

VS overvoltage

warning flag

VDD overvoltage

flag

Thermal

warning flag

Thermal

shutdown flag

Fail-safe

input not

bit

Charge

pump not

ready bit

Bit

Name

Description

VDHOV

VDH overvoltage flag. This flag is set and latched as soon as an overvoltage is detected on VDH

supply. It can be cleared by SPI, only if the source of the fault is no longer present.

VDHUV

VDH undervoltage flag. This flag is set and latched as soon as an undervoltage is detected on

VDH supply. It can be cleared by SPI, only if the source of the fault is no longer present.

VSOVW

VS overvoltage warning flag. This flag is set and latched as soon as an overvoltage is detected

on VS supply. It can be cleared by SPI, only if the source of the fault is no longer present.

VDDOV

VDD overvoltage flag. This flag is set and latched as soon as an overvoltage is detected on VDD

supply. It can be cleared by SPI, only if the source of the fault is no longer present.

Thermal warning flag. This flag is set and latched as soon as device junction temperature

exceeds TW threshold for a time longer than the corresponding filtering time. It can be cleared by

SPI, only if the source of the fault is no longer present.

TSD

Thermal shutdown flag. This flag is set and latched as soon as device junction temperature

exceeds TSD threshold for a time longer than the corresponding filtering time. It can be cleared

by SPI, only if the source of the fault is no longer present.

FSIN

Fail-safe input not bit. This bit is the logic OR of DSR2 bits from BIT7 to BIT11. It is automatically

set anytime the FSINB pin is pulled low for a time longer than the corresponding analog filtering

time (tFSINB_filt) and automatically reset anytime the FSINB pin is pulled high for a time longer

than the analog filtering time and FSINHS1=FSINHS2=FSINLS1=FSINLS2=0. It is a read only

bit, so it cannot be cleared by SPI. In case the FSINB pin is left floating, because of the internal

pull-down at the FSINB pin, the value of this bit will be automatically set to one.

NRDY

Charge pump not ready bit. This bit is automatically set anytime the charge-pump is enabled and

automatically reset a filtering time (tCP) after its output voltage reaches CPLOW threshold

(VCP_low). It is a read only bit, so it cannot be cleared by SPI.

Table 45. Status register DSR1 (0x01) LSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (R/C)

(1)

0 (R/C)

CPLOW

WDGF

DIOOV

DSHS1

DSLS1

DSHS2

DSLS2

Charge

pump

low

flag/bit

Watchdog

fault flag

Digital IO

overvoltage flag

VDS monitoring flags

Parity bit

Bit

Name

Description

CPLOW

Charge pump low flag/bit. If CP_LOW_CONFIG control bit is set to one, the CPLOW is a read only

status bit automatically set as soon as the charge pump output voltage falls below CPLOW threshold

(VCP_low) for a time longer than the corresponding filtering time (tCP) and automatically reset as soon

as the charge pump output voltage rises back above CPLOW threshold for a time longer than the

filtering time.

If CP_LOW_CONFIG control bit is set to zero, the CPLOW is a read & clear status flag set and latched

as soon as the charge pump output voltage falls below CPLOW threshold (VCP_low) for a time longer

than the corresponding filtering time. The CLOW flag can be cleared by SPI, only if the source of the

fault is no longer present.

L99H92

Status registers

DS14069 - Rev 4

page 51/77

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