L99H92 datasheet(52/77 Pages) STMICROELECTRONICS

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Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

WDGF

Watchdog fault flag. This flag is set and latched as soon as a watchdog fault is detected. The flag can

be cleared by proper SPI Read & Clear command.

DIOOV

Digital IO overvoltage flag. This flag is set and latched as soon as an overvoltage is detected on any of

the following digital input/output pins: PWM/IN1, DIR/IN2, DIAGN, CSO1, CSO2, CSN, SDI, SDO, CLK.

It can be cleared by SPI, only if the source of the fault is no longer present.

DSHS1

VDS monitoring flags. Flag DSxSn (x=L,S / n=1,2) is set and latched as soon as the VDS of the

corresponding MOSFET exceeds the relative threshold (set by DSMON[3:0] bits) for a time longer than

the corresponding filtering time or blanking plus filtering time, where the blanking time is applicable. It

can be cleared by SPI, only if the source of the fault is no longer present.

DSLS1

DSHS2

DSLS2

1. The CPLOW is a Read & Clear status flag or a read only status bit depending on the value of the control bit

CP_LOW_CONFIG.

Table 46. Status register DSR2 (0x02) MSB

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

0 (R)

RES

FSINLL

FSINHS1

FSINLS1

FSINHS2

Reserved

bit

Reserved

bit

Reserved bit

Fail-safe

input not logic

level bit

Fail-safe input

not effect on

HS1 bit

Fail-safe input

not effect on

LS1 bit

Fail-safe input

not effect on

HS2 bit

Bit

Name

Description

RES

Reserved

RES

Reserved

RES

Reserved

RES

Reserved

FSINLL

Fail-safe input not logic level bit. This bit reflects the inverted logic level of the FSINB pin taking into

account the corresponding analog filtering time (tFSINB_filt). This bit is automatically set anytime the

FSINB pin is pulled low for a time longer than the corresponding filtering time and automatically reset

anytime the FSINB pin is pulled high for a time longer than the filtering time. It is a read only bit, so it

cannot be cleared by SPI. In case the FSINB pin is left floating, because of the internal pull-down at

the FSINB pin, the bit is automatically set to one.

FSINHS1

Fail-safe input not effect on HS1 bit. This bit indicates whether the HS1 gate driver is configured in sink

switch mode (FSINHS1=1) because of the FSINLL set to one or not (FSINHS1=0). In case of no faults

the FSINHS1 bit should be automatically set once the FSINLL is set and automatically reset once the

FSINLL is reset. It is a read only bit, so it cannot be cleared by SPI.

FSINLS1

Fail-safe input not effect on LS1 bit. This bit indicates whether the LS1 gate driver is configured in sink

switch mode (FSINLS1=1) because of the FSINLL set to one or not (FSINLS1=0). In case of no faults

the FSINLS1 bit should be automatically set once the FSINLL is set and automatically reset once the

FSINLL is reset. It is a read only bit, so it cannot be cleared by SPI.

FSINHS2

Fail-safe input not effect on HS2 bit. This bit indicates whether the HS2 gate driver is configured in sink

switch mode (FSINHS2=1) because of the FSINLL set to one or not (FSINHS2=0). In case of no faults

the FSINHS2 bit should be automatically set once the FSINLL is set and automatically reset once the

FSINLL is reset. It is a read only bit, so it cannot be cleared by SPI.

L99H92

Status registers

DS14069 - Rev 4

page 52/77

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