L99H92 datasheet(15/77 Pages) STMICROELECTRONICS

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2.8

Fail-safe output switch-off input not pin (FSINB)

The L99H92 features an asynchronous, logic independent fail-safe input pin working as a redundant switch-off

path for all MOSFETs. The fail-safe input not pin (FSINB), active low, has an internal pull-down resistance

RFSINB. As soon as the FSINB pin falls below the VFSINBLTH threshold for a time longer than tFSINB_filt, the

FSINLL status bit together with the FSIN status bit are set and the device is put in fail-safe mode. In fail-safe

mode the OUTE control bit is reset and the gate drivers are forced in sink switch mode to switch off actively all the

MOSFETs with the maximum available current, regardless of the programmed gate discharge current (SLEWDx

control bits). As long as the FSINB input pin is low, the gate drivers are forced in sink switch mode and the OUTE

control bit is forced to zero. For functional safety reasons, the FSINHS1,2 and the FSINLS1,2, status bits indicate

whether the HS1,2 and the LS1,2, gate drivers have been put successfully in sink switch mode or not, because of

the FSINB pin pulled low. Once the FSINB pin has been pulled low, in order to reactivate again the gate drivers

that are forced in sink switch mode, the FSINB pin has to rise above the VFSINHTH threshold for a time longer

than the filtering time. All the FSINHSx and the FSINLSx status bits have to go back to zero (indicating that all the

gate drivers came out of forced sink switch mode and making the device come out of fail-safe mode) and then the

OUTE control bit has to be set back to one via SPI. In case where at least one of the status bits FSINHSx or

FSINLSx remains set, indicating that at least one gate driver did not come out of forced sink switch mode, the

device remains in fail-safe mode. With the FSINB pin high and the OUTE control bit reset, the gate drivers are

disabled, leaving just a resistive link between gate and source of each MOSFET.

The FSINB input pin status can be read, but not cleared, through FSINLL status bit. The FSIN status bit, linked to

the global status byte fail-safe bit (FS), is the logical OR of the following status bits: FSINLL, FSINHS1, FSINLS1,

FSINHS2, and FSINLS2. The fail-safe input pin acts just on the gate drivers and on the OUTE control bit.

2.9

Diagnostic not output (DIAGN)

The microcontroller can use the DIAGnostic not (DIAGN) output pin, active low, to detect a device fault, including

a device power-on-reset event. The purpose of the DIAGN output pin is to warn immediately the microcontroller

that a new fault has been detected by the device, without the need of periodic SPI transfers. The DIAGN output

pin has an internal weak pull-up resistance (RDIAGN). The logic level signal at the pin is the logical NOR

combination of all the status flags and status bits linked to the pin through the DIAGCR control register, together

with the global status byte RSTB bit. Once the device comes out of standby mode, the DIAGN pin is pulled low

because of the global status byte RSTB bit. If just the global status byte RSTB bit is set, any valid SPI

communication frame clears the RSTB bit pulling up the DIAGN pin. Any read access to the DSR1 register resets

this signal to high level, until an error coming from a new source occurs pulling again the pin low. If a fault coming

from a new error source occurs during the read access to the DSR1 register, the DIAGN output pin remains low

(this avoids any loss of information since the new error source status flag/bit will not be reported by the

concomitant read access, but a new read access would be required). Even if a read operation of the status

DSR1 will pull the DIAGN pin high. If a new source of fault triggers an error during the Read & Clear access to the

DSR1 register, the Read & clear operation will not pull the DIAGN pin high at the CSN rising edge of the DSR1

will not be reported by the concomitant Read & Clear access, but a new read or Read & Clear access would be

required).

2.10

Current monitors

The current sense amplifiers (CSA1 and CSA2) are designed for current sensing in automotive applications. They

are independent, bidirectional, single-supply differential amplifiers with a wide input common mode voltage range

(VICM). They support high-side current sensing, low side-current sensing and in-line current sensing through two

sensing resistors.

A gain of 100, 50, 20 or 10 is independently SPI programmable for each CSA. Since the CSAs have a trans-

conductance input stage, input series resistors (for filtering etc.) should not exceed 50 Ω to keep the additional

gain error below 1%.

The CSO outputs are compliant to the VDD power supply rail and have a programmable offset set by CSA1OO

and CSA2OO control bits. If these bits are reset, the output offset is set to VO0, otherwise it is set to VO1. The

current sense amplifiers input stage is supplied by the charge pump. When the charge pump is disabled, the

CSAs is disabled as well.

By default, both current sense amplifiers are enabled. To reduce current consumption both of them can be

disabled independently through control bits DCSA1 and DCSA2.

L99H92

Fail-safe output switch-off input not pin (FSINB)

DS14069 - Rev 4

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