L99H92 datasheet(54/77 Pages) STMICROELECTRONICS

54 / 77 page

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

OUTE

Outputs enable control bit. Assuming that the FSINB pin is high, if this bit is reset, all the gate

drivers are disabled and the MOSFTEs are passively shut down through the internal

resistance connected between gate and source. Assuming that the FSINB pin is high, if this

bit is set, all the gate drivers are enabled and the MOSFETs are turned on/off according to

Table 2 or Table 3 depending on the INPMODE control bit value. Assuming the device in

active mode, when the FSINB pin goes low, the MOSFETs gate drivers are forced in sink

switch mode and the OUTE control bit is reset. While the FSINB pin is low, the OUTE control

bit value is frozen and cannot be changed via SPI.

When a watchdog fault occurs, setting the WDGF flag, the OUTE control bit is reset. While

the WDGF flag is set, the OUTE control bit value is frozen and cannot be changed via SPI.

AFWE

Active free-wheeling enable control bit. In case INPMODE is reset, this bit enables/disables

active free-wheeling. When set it enables the active free-wheeling. When reset it disables the

active free-wheeling. In case INPMODE is set, this bit has no effect.

FWS

Free-wheeling selection control bit. In case INPMODE is reset and active free-wheeling is

enabled (AFWE=1), this bit sets whether the active free-wheeling is performed on high side

(FWS=1) or on low-side (FWS=0). In case INPMODE is reset and active free-wheeling is

disabled (AFWE=0), this bit sets whether the passive free-wheeling is performed on high side

(FWS=1) or on low-side (FWS=0).In case INPMODE is set, this bit has no effect.

DIS1

Disable leg1,2 control bits. In case INPMODE is set, these bits switch-off both the external

MOSFETs of leg 1 (DIS1=1) and/or leg 2 (DIS2=1). In case INPMODE is reset, these bits

have no effect.

DIS2

DSMON_CONFIG

DSMonitoring configuration control bit. In case this bit is set and INPMODE is reset, any VDS

monitoring fault will actively switch off all the full-bridge MOSFETs by configuring all the gate

drivers in sink switch mode. In all the other cases INPMODE=1 or INPMODE=0 with

DSMON_CONFIG=0 just the affected/offended half-bridge MOSFETs are actively switched

off configuring the corresponding gate drivers in sink switch mode.

OLH1L2

Open load in off-state control bit. This bit is really taken into account only when OUTE is

reset, otherwise it is discarded (and related circuitry is disconnected from device power

outputs). See Table 4. Full-bridge monitoring in off-mode.

1. The INPMODE will be a read only or a read and write control bit depending on the value of the control bit OUTE.

2. The OUTE is a read only or a read and write control bit depending on the logic level at the input pin FSINB and on the status

flag WDGF value.

Table 49. Control register DCR (0x03) LSB

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (R/W)

0 (R)

OLH2L1

OLTHH

CP_LOW_CONFIG

CPFDD

OVTS

RES

Open

load in

off-state

bit

Off-state diagnostic

comparator

threshold selection

bit

Charge pump low

configuration bit

Charge

pump

frequency

dithering

disable bit

Overvoltage

threshold

selection bit

Reserved bit Reserved bit

Parity

Bit

Name

Description

OLH2L1

Open load in off-state control bit. This bit is really taken into account only when OUTE is reset,

otherwise it is discarded (and related circuitry is disconnected from device power outputs).

See Table 4. Full-bridge monitoring in off-modering in off-mode

OLTHH

Off-state diagnostic comparator threshold selection bit. The off-state diagnostic comparator

threshold is set to 1/6VDH for OLTHH reset and to 5/6VDH for OLTHH set. See Table 4. Full-

bridge monitoring in off-mode

CP_LOW_CONFIG

Charge pump low configuration control bit. Setting this bit, CPLOW status flag/bit behaves as

a read only status bit and the outputs are re-activated automatically upon recovery of the

charge pump output voltage.

If this bit is reset, CPLOW status flag/bit behaves as a read & clear status flag so that the

outputs are disabled until the CPLOW status flag is cleared. In this latter case, the charge

pump output voltage has to rise above VCP_low for a time longer than the corresponding

filtering time and CPLOW status flag has to be reset to re-enable device outputs.

L99H92

Control registers

DS14069 - Rev 4

page 54/77

L99H92 Datasheet(PDF) 54 Page - STMicroelectronics

L99H92 Datasheet(HTML) 54 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL