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L99H92 Datasheet(PDF) 58 Page - STMicroelectronics |
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L99H92 Datasheet(HTML) 58 Page - STMicroelectronics |
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58 / 77 page  Table 56. Control register GD2CR2 (0x07) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R) 0 (R) 0 (R) 0 (R) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R) RES RES RES RES DSMON2[2] DSMON2[1] DSMON2[0] RES Reserved bit Reserved bit Reserved bit Reserved bit VDS monitoring threshold configuration bits Reserved bit Bit Name Description 15 RES Reserved 14 RES 13 RES 12 RES 11 DSMON2[2] VDS monitoring threshold configuration control bits for the leg 2 in case INPMODE are set. These bits have no effect if INPMODE is reset. 000=0.075V 001=0.15V 010=0.25V 011=0.4V 100=0.6V 101=0.8V 110=1V 111=1.2V 10 DSMON2[1] 9 DSMON2[0] 8 RES Table 57. Control register GD2CR2 (0x07) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R/W) 0 (R/W) 0 (R/W) 0 (R) 0 (R/W) 0 (R/W) 0 (R) DSBT2[2] DSBT2[1] DSBT2[0] RES FT2[1] FT2[0] RES P VDS monitoring blanking time configuration bits Reserved bit VDS monitoring filter time configuration bits Reserved bit Parity bit Bit Name Description 7 DSBT2[2] VDS monitoring blanking time configuration control bits for the leg 2 in case INPMODE are set. These bits have no effect if INPMODE is reset. Blanking time in µs = DSBT2[2:0] + 1 (min= 1 µs, max= 8 µs) 6 DSBT2[1] 5 DSBT2[0] 4 RES Reserved 3 FT2[1] VDS monitoring filtering time configuration control bits for the leg 2 in case INPMODE are set. These bits have no effect if INPMODE is reset. Filter time in µs = (FT2[1:0] + 1)*1.5 (min= 1.5 µs, max= 6 µs) 2 FT2[0] 1 RES Reserved 0 P Parity bit Table 58. Control register CSCR (0x08) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R) 0 (R/W) 0 (R/W) 0 (R) 0 (R/W) 0 (R) 0 (R/W) 0 (R) RES GCSA1[1] GCSA1[0] RES DCSA1 RES CSA1OO RES L99H92 Control registers DS14069 - Rev 4 page 58/77 |
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