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L99H92 Datasheet(PDF) 62 Page - STMicroelectronics |
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L99H92 Datasheet(HTML) 62 Page - STMicroelectronics |
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62 / 77 page ![]() Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Bit Name Description 15 RES Reserved 14 RES 13 RES 12 RES 11 RES 10 RES 9 RES 8 RES Table 65. Watchdog trigger/disable register WDGTRDIS (0x0A) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register read access 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) 0 (R) RES RES RES WDGSTATUS WDGINF2] WDGINF[1] WDGINF[0] P Reserved bit Reserved bit Reserved bit Watchdog status bit Watchdog information bits Parity bit Bit Name Description 7 RES Reserved 6 RES 5 RES 4 WDGSTATUS Watchdog status bit. This bit is set if the watchdog has been successfully disabled. This bit is reset if the watchdog is enabled. 3 WDGINF[2] Watchdog information bits. These bits represent the three least significant bits of the latest write command performed on the same register. For example, they will return ”101" after first trigger WDGTRDIS[15:1]=5555h, then ”010" after second trigger WDGR[15:1]=2AAAh. It will return "”111" after writing the second key WDGR[15:1]=1097h. Since no other SPI transfer should fall between the two words that form the key during the procedure to disable the watchdog, ”011" shall not be read after first part of the key write command WDGR[15:1]=2F6Bh, otherwise the disabling procedure will be aborted generating a watchdog fault. 2 WDGINF[1] 1 WDGINF[0] 0 P Parity bit Table 66. Reserved bits RESVDO (0x0B) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) RES_RW_14 RES_RW_13 RES_RW_12 RES_RW_11 RES_RW_10 RES_RW_9 RES_RW_8 RES_RW_7 Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Reserved bit Bit Name Description 15 RES_RW_14 Reserved 14 RES_RW_13 13 RES_RW_12 12 RES_RW_11 11 RES_RW_10 L99H92 Control registers DS14069 - Rev 4 page 62/77 |
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