L99H92 datasheet(26/77 Pages) STMICROELECTRONICS

26 / 77 page

The binary value of WT[5:0] times 5 ms indicates the maximal safe long open window time. CW[3:0] times 5 ms

defines the maximum closed window time and WW[1:0] times 5 ms defines the minimum safe open window time.

The watchdog trigger register address is defined by the <WD bit pos. 1> ROM register.

Device application registers (RAM)

The Device Application Registers are all registers accessible using OpCode ‘00’, ‘01’ and ‘10’. The functions of

these registers are defined in the device specification.

Protocol failure detection

To achieve a communication protocol that covers certain fail-safe requirements a basic set of SPI communication

failure detection mechanisms is implemented.

Clock monitor

During communication (CSN low) a clock monitor counts the valid CLK clock edges. If the CLK edges do not

correlate with the SPI Data Length an SPIE is reported with the next command and the actual command is

rejected.

By accessing the Device Information Registers (OpCode = ‘11’) the Clock Monitor is set to a minimum of 24 CLK

edges plus a multiple by 16 (for example, 16, 32, , …).

Providing no CLK edge during the CSN low phase is not recognized as an SPIE. For an SPI Burst Read also the

SPI Data Length plus multiple numbers of Payloads CLK edges are assumed as a valid communication.

CLK polarity (CPOL) check

To detect the wrong polarity access via CLK the internal clock monitor is used. Providing first a negative edge on

CLK during communication (CSN low) or a positive edge at last will lead to an SPI Error reported in the next

communication and the actual command is rejected.

CLK phase (CPHA) check

To verify that the CLK Phase of the SPI master is set correctly a special Device Information Register is

implemented. By reading this register the data must be 55H. In case AAH is read, the CPHA setting of the SPI

master is wrong and a proper communication cannot be guaranteed.

CSN timeout

By pulling CSN low the SDO is set active and leaves its tristate condition. To ensure communication between

other SPI devices within the same bus even in case of CSN stuck @ low a CSN timeout is implemented. By

pulling CSN low an internal timer is started. When the timer reaches its end, the ongoing command is rejected,

the SPIE is set (and it will be visible at the next communication) and the SDO is set in tristate condition.

SDI stuck at LOW

As a communication with data all-‘0’ and OpCode ‘00’ on address b’000000 cannot be distinguished between a

valid command and a SDI stuck @ LOW, this communication is not allowed. Nevertheless, in case a stuck @

LOW is detected the command will be rejected and the SPIE will be set and it will be visible at the next

communication.

SDI stuck at HIGH

As a communication with data all-‘1’ and OpCode ‘11’ on address b’111111 cannot be distinguished between a

valid command and a SDI stuck @ HIGH, this communication is not allowed. In case a stuck @ HIGH is detected

the command will be rejected and the SPIE will be set and it will be visible at the next communication.

SDO stuck @

The SDO stuck @ GND and stuck @ HIGH have to be detected by the SPI master. As the definition of the GSB

guarantees at least one toggle, a GSB with all ‘0’ or all ‘1’ reports a stuck at error.

L99H92

ST SPI 4.1

DS14069 - Rev 4

page 26/77

L99H92 Datasheet(PDF) 26 Page - STMicroelectronics

L99H92 Datasheet(HTML) 26 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL