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L99H92 Datasheet(PDF) 55 Page - STMicroelectronics |
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L99H92 Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 77 page  Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 4 CPFDD Charge pump frequency dithering disable control bit. If this bit is set the charge pump frequency dithering is disabled, otherwise it is enabled. 3 OVTS Overvoltage threshold selection control bit. In case this bit is reset, the VS/VDH overvoltage threshold is set to VSOVWT1/ VDHOVT1, otherwise it is set to VSOVWT2/ VDHOVT2. 2 RES Reserved 1 RES Reserved 0 P Parity Table 50. Control register GD1CR1 (0x04) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) SLEWC1[4] SLEWC1[3] SLEWC1[2] SLEWC1[1] SLEWC1[0] DT1[3] DT1[2] DT1[1] Gate charge current configuration bits Dead-time configuration bits Bit Name Description 15 SLEWC1[4] Gate charge current configuration bits for the full-bridge (INPMODE=0) or for leg 1 (INPMODE=1). SLEWC1[4:0]=n sets gate charge current to n x IGMAX/31. Setting SLEWC1[4:0]=0 disables gate charge current control and enables gate charging through low impedance switches. 14 SLEWC1[3] 13 SLEWC1[2] 12 SLEWC1[1] 11 SLEWC1[0] 10 DT1[3] Dead-time configuration control bits for the full-bridge (INPMODE=0) or for leg 1 (INPMODE=1). 0000=250ns 0001=500ns 0010=750ns 0011=1000ns 0100=1250ns … 1110=3750ns 1111=4000ns 9 DT1[2] 8 DT1[1] Table 51. Control register GD1CR1 (0x04) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R/W) 0 (R) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) DT1[0] RES SLEWD1[4] SLEWD1[3] SLEWD1[2] SLEWD1[1] SLEWD1[0] P Dead-time configuration bit Reserved bit Gate discharge current configuration bits Parity bit Bit Name Description 7 DT1[0] Dead-time current configuration control bit for the full-bridge (INPMODE=0) or for leg 1 (INPMODE=1). 6 RES Reserved 5 SLEWD1[4] Gate discharge current configuration bits for the full-bridge (INPMODE=0) or for leg 1 (INPMODE=1). SLEWD1[4:0]=n sets gate discharge current to n x IGMAX/31. Setting SLEWD1[4:0]=0 disables gate discharge current control and enables gate discharging through low impedance switches. 4 SLEWD1[3] 3 SLEWD1[2] L99H92 Control registers DS14069 - Rev 4 page 55/77 |
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