L99H92 datasheet(7/77 Pages) STMICROELECTRONICS

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2.1.4

VDD overvoltage (VDDOV)

When the VDD exceeds the VDDOV threshold for a time longer than tovuv_filt, then the corresponding overvoltage

flag (VDDOV) is set, and to protect the application all the gate drivers are forced in sink switch mode to switch off

actively all the MOSFETs with the maximum available current, regardless of the programmed gate discharge

current (SLEWDx control bits). The gate drivers come out of forced sink switch mode once the overvoltage flag

VDDOV is cleared. The overvoltage flag VDDOV can be cleared by an SPI “Read & Clear” command only if the

VDD overvoltage condition is no longer present, namely if VDD<VDDOV for a time longer than the corresponding

filtering time tovuv_filt. The VDD overvoltage protection aims at making the application robust against VDD short to

battery.

2.1.5

Digital input/output overvoltage (DIOOV)

When the voltage at any of the digital input/output pins listed below exceeds the VDIOOV threshold for a time

longer than tovuv_filt, then the corresponding overvoltage flag (DIOOV) is set, and to protect the application all the

gate drivers are forced in sink switch mode to switch off actively all the MOSFETs with the maximum available

current, regardless of the programmed gate discharge current (SLEWDx control bits). The gate drivers come out

of forced sink switch mode once the overvoltage flag DIOOV is cleared. The overvoltage flag DIOOV can be

cleared by an SPI “Read & Clear” command only if the digital input/output overvoltage condition is no longer

present namely if VDIO<VDIOOV for a time longer than the corresponding filtering time tovuv_filt. The digital input/

output overvoltage protection aims to make the application robust against digital input/output pins short to battery.

The digital input/output pins monitored for overvoltage events are: PWM/IN1, DIR/IN2, DIAGN, CSO1, CSO2,

CSN, SDI, SDO, CLK. Any overvoltage detection affecting the device digital output pins DIAGN and SDO will not

affect/propagate internally to VDD. Anyhow, all the digital input/output pins, FSINB pin and EN pin included, can

withstand a short to battery up to the related absolute maximum rating (see Table 17).

2.1.6

Power-on reset (POR)

The device gets out of standby mode to get into active mode as soon as the EN pin is high, the VDD is above

VDDPOR_OFF and the VS is above VSPOR_OFF.

If either the VDD falls below VDDPOR_ON or the VS falls below VSPOR_ON with the EN pin still high, the device

experiences a power-on reset and enter in standby mode. In standby mode the gate drivers and the charge pump

are switched off, leaving just the internal resistive link between gate and source at each MOSFET (RGSHx and

RGSLx). Besides, the content of all the registers is reset to default value. Once out of standby mode the global

status byte RSTB bit will be set indicating that all the device registers have been reset to default value. This bit is

automatically cleared by any valid SPI communication frame.

2.2

Standby mode (EN)

The L99H92 is enabled/disabled by pulling the EN input pin high/low. If VDD > VDDPOR_OFF, VS>VSPOR_OFF and

EN input pin is high, the device enters in active mode. If any of the above conditions is not met, the device will

remain in standby mode. When the EN input pin is left floating, because of the internal pull-down current (IIN), the

device enters (if not already) in standby mode minimizing its current consumption. In standby mode the minimum

current drawn by VS, less than 5 μA (ISq) for CSN = high (SDO in tristate), can be achieved by pulling the EN

input pin low. Besides, in standby mode, the gate drivers together with the charge pump are switched off. All the

MOSFETs are passively switched off by the internal resistive link between gate and source present at each

MOSFET (regardless of the control input pins PWM/IN1, DIR/IN2 and FSINB logic levels), and all the registers

are reset to default values. Out of standby mode the device diagnostic is available and all the operations on the

device registers are available as well.

2.3

Active mode (OUTE)

As soon as the EN pin is high, the VDD is above VDDPOR_OFF and the VS is above VSPOR_OFF the device comes

out of standby mode to go in active mode. In active mode the device diagnostic is available.

In active mode with no faults, the charge pump is enabled, and the gate drivers are enabled as long as the OUTE

control bit is set. Instead, if the OUTE control bit is reset, then all the gate drivers are disabled and all the

MOSFETs are switched off passively through the internal resistive connection between gate and source present

at each MOSFET. In active mode with no fault and with OUTE set, the MOSFETs to be turned on are controlled

through the combination of the input signals PWM/IN1, DIR/IN2 and the control bits INPMODE, AFWE and FWS.

L99H92

Standby mode (EN)

DS14069 - Rev 4

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