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L99H92 Datasheet(PDF) 59 Page - STMicroelectronics |
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L99H92 Datasheet(HTML) 59 Page - STMicroelectronics |
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59 / 77 page ![]() Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Reserved bit CSA1 gain selection bits Reserved bit CSA1 disable bit Reserved bit CSA1 output offset bit Reserved bit Bit Name Description 15 RES Reserved 14 GCSA1[1] CSA1 gain selection control bits. 00=10 01=20 10=50 11=100 13 GCSA1[0] 12 RES Reserved 11 DCSA1 CSA1 disable control bit. If this control bit is set the CSA1 is disabled, otherwise it is enabled. 10 RES Reserved 9 CSA1OO CSA1 output offset control bit. If this bit is reset, the output offset is set to VO0, otherwise it is set to VO1. 8 RES Reserved Table 59. Control register CSCR (0x08) LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 (R) 0 (R/W) 0 (R/W) 0 (R) 0 (R/W) 0 (R) 0 (R/W) RES GCSA2[1] GCSA2[0] RES DCSA2 RES CSA2OO P Reserved bit CSA2 gain selection bits Reserved bit CSA2 disable bit Reserved bit CSA2 output offset bit Parity bit Bit Name Description 7 RES Reserved 6 GCSA2[1] CSA2 gain selection control bits. 00=10 01=20 10=50 11=100 5 GCSA2[0] 4 RES Reserved 3 DCSA2 CSA2 disable control bit. If this control bit is set the CSA2 is disabled, otherwise it is enabled. 2 RES Reserved 1 CSA2OO CSA2 output offset control bit. If this bit is reset, the output offset is set to VO0, otherwise it is set to VO1. 0 P Parity bit Table 60. Diagnostic control register DIAGCR (0x09) MSB Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) 0 (R/W) DGVDHOVE DGVDHUVE DGVSOVWE DGVDDOVE DGTWE DGTSDE DGFSINE DGNRDYE Diagnostic output VDHOV enable bit Diagnostic output VDHUV enable bit Diagnostic output VSOVW enable bit Diagnostic output VDDOV enable bit Diagnostic output TW enable bit Diagnostic output TSD enable bit Diagnostic output FSIN enable bit Diagnostic output NRDY enable bit L99H92 Control registers DS14069 - Rev 4 page 59/77 |
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