THP210 datasheet(33/45 Pages) TI2

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11 Layout

11.1 Layout Guidelines

11.1.1 Board Layout Recommendations

• Keep differential signals routed together to minimize parasitic impedance mismatch.

• Connect a 0.1-µF capacitor to the supply nodes through a via.

• If no external voltage is used, connect a 0.1-µF capacitor to the VOCM pin.

• Keep any high-frequency nodes that can couple through parasitic paths away from the VOCM node.

• Clean the printed circuit board (PCB) after assembly to minimize any leakage paths from excess flux into the

VOCM node.

11.2 Layout Example

±IN

VS+

VOCM

OUT+

+IN

VSí

CCM

CVS+

Connect the powerdown pin

through a via. If powerdown is

not needed, leave floating.

Route the VOCM pin connection

through a via. Connect a 0.1 µF

capacitor to VOCM if no external

voltage is used to set the output

common mode voltage.

Connect IN+/IN± through input

resistors on the top layer.

Maintain symmetry between

traces and routing to minimize

common mode coupling.

Connect bypass capacitors

through a via.

VVS+

THP210

2 k

VVOCM

2 k

VVS±

VPD

VOUT+

VOUT±

VOUT

OUTí

CCM

CVS+

CVSí

VOUT+

VINí

VIN+

VOUT±

CVSí

GND

VOUT±

VINDIFF / 2

Figure 11-1. Example Layout

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THP210

SBOS932C – JANUARY 2020 – REVISED MARCH 2021

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