VDD

SENSE

OUT

VIT+

VHYS

t pd(LH)

t pd(LH)

t pd(HL)

VIT±

t

d(start)

V(POR)

6

TLV6703

SBOS865B – JANUARY 2018 – REVISED NOVEMBER 2019

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(1)

High-to-low and low-to-high refers to the transition at the input pin (SENSE).

(2)

During power on, VDD must exceed 1.8 V for at least 150 µs before the output is in a correct state.

7.6 Timing Requirements

over operating temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

tpd(HL)

High-to-low propagation delay (1)

VDD = 5 V, 10-mV input overdrive,

RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,

see Figure 1

18

µs

tpd(LH)

Low-to-high propagation delay (1)

VDD = 5 V, 10-mV input overdrive,

RP = 10 kΩ, VOH = 0.9 × VDD, VOL = 400 mV,

see Figure 1

29

µs

td(start)

Start-up delay (2)

150

µs

7.7 Switching Characteristics

over operating temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tr

Output rise time

VDD = 5 V, 10-mV input overdrive,

RP = 10 kΩ, VO = (0.1 to 0.9) × VDD

2.2

µs

tf

Output fall time

VDD = 5 V, 10-mV input overdrive,

RP = 10 kΩ, VO = (0.1 to 0.9) × VDD

0.22

µs

Figure 1. Timing Diagram