10

TLV6703

SBOS865B – JANUARY 2018 – REVISED NOVEMBER 2019

www.ti.com

Product Folder Links: TLV6703

Submit Documentation Feedback

Copyright © 2018–2019, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Input Pin (SENSE)

The TLV6703 comparator has two inputs: one external input, and one input internally connected to the internal

400mV reference. The comparator rising threshold is trimmed to be equal to the reference voltage (400 mV). The

comparator also has a built-in falling hysteresis that makes the device less sensitive to supply-rail noise and

provides stable operation.

The comparator input (SENSE) is able to swing from ground to 6.5 V, regardless of the device supply voltage.

Although not required in most cases, to reduce sensitivity to transients and layout parasitics for extremely noisy

applications, place a 1-nF to 10-nF bypass capacitor at the comparator input.

OUT is driven to logic low when the input SENSE voltage drops below (VIT-). When the voltage exceeds VIT+, the

output (OUT) goes to a high-impedance state; see Figure 1.

8.3.2 Output Pin (OUT)

In a typical TLV6703 application, the output is connected to a GPIO input of the processor (such as a digital

signal processor [DSP], central processing unit [CPU], field-programmable gate array [FPGA], or application-

specific integrated circuit [ASIC]).

The TLV6703 device provides an open-drain output (OUT). Use a pullup resistor to hold this line high when the

output goes to high impedance (not asserted). To connect the output to another device at the correct interface-

voltage level, connect a pullup resistor to the proper voltage rail. The TLV6703 output can be pulled up to 18 V,

independent of the device supply voltage.

Table 2 and the Input Pin (SENSE) section describe how the output is asserted or de-asserted. See Figure 1 for

a timing diagram that describes the relationship between threshold voltage and the respective output.

8.3.3 Immunity to Input-Pin Voltage Transients

The TLV6703 is relatively immune to short voltage transient spikes on the sense pin. Sensitivity to transients

depends on both transient duration and amplitude; see Figure 7, Minimum Pulse Width vs Threshold Overdrive

Voltage.

8.4 Device Functional Modes

8.4.1 Normal Operation (VDD > UVLO)

When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUT signal correspond to the voltage on

SENSE as listed in Table 2.

8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO)

When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage,

V(POR), the OUT signal is asserted regardless of the voltage on SENSE.

8.4.3

Power-On Reset (VDD < V(POR))

When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)),

SENSE is in a high-impedance state.