NC

VDD1

GND

TPS3430

VDD2

3.3V

Microcontroller

SET1

V

CORE

CRST

GND

WDO

NMI

CWD

SET0

WDI

GPIO

NC

5nF

GND

Open-drain Buffer

Figure 8-9. Monitoring Microcontroller Using a Latching Window Watchdog Timer

8.2.3.1 Design Requirements - Design 3

PARAMETER

DESIGN REQUIREMENT

DESIGN RESULT

Watchdog Reset delay

Latch WDO upon watchdog fault

Latching watchdog functionality that keeps WDO

logic low when fault occurs

Watchdog window

Functions with a 1-Hz pulse-width modulation

(PWM) signal with a 50% duty cycle

Leaving the CWD pin unconnected with SET0 = 1

and SET1 = 1 produces a window with a tWDL(max)

of 920 ms and a tWDU(min) of 1360 ms

Output logic voltage

3.3-V Open-Drain

3.3-V Open-Drain

Maximum device current

consumption

200 µA

10 µA of current consumption, typical worst-case of

199 µA when WDO is asserted

8.2.3.2 Detailed Design Procedure - Design 3

8.2.3.2.1 Meeting the Latching Output Requirement - Design 3

To achieve the latching watchdog feature, an open-drain buffer is connected from WDO to CRST with a small

value capacitor connected from the Anode of the buffer connected to CRST to GND. The capacitor must be a

small value to prevent additional delay when triggering WDO to active low during watchdog fault. A capacitor

between 150 pF and 5 nF is recommended.

In Figure 8-10 below, the latching watchdog feature is shown by causing a watchdog fault and observing WDO.

Because no pulse arrived on WDI within the Watchdog Timeout, WDO activates and goes logic low and remains

low. To reset the watchdog, the device must be restarted by dropping VDD below VDD (min).

8.2.3.2.2 Setting the Watchdog Window - Design 3

The Watchdog Window is set via the CWD, SET0, and SET1 pin configurations. To achieve a Watchdog Timeout

of 1 second corresponding to a 1-Hz WDI signal, this design simply leaves CWD pin floating (NC - No Connect)

and ties SET0 and SET1 to VDD to set the SET pins to logic high. With this configuration, the Watchdog Lower

Boundary tWDL (typ) is set for 800 ms and the Watchdog Upper Boundary tWDU (typ) is set for 1.6 seconds. Refer to

Table 6.6 Timing Requirements to see the factory-programmed window watchdog timing configurations.

TPS3430

SBVS366A – JULY 2018 – REVISED OCTOBER 2021

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