7.3.2.1.1 Enabling the Window Watchdog

The TPS3430 features the ability to enable and disable the watchdog timer. This feature allows the user to start

with the watchdog timer disabled and then enable the watchdog timer using the SET0 and SET1 pins. The

ability to enable and disable the watchdog is useful to avoid undesired watchdog trips during initialization and

shutdown. When the SETx pins are changed to disable the watchdog timer, changes on the pins are responded

to immediately (as shown in Figure 7-2). When the watchdog goes from disabled to enabled, there is a 150 μs

(tWD-setup) transition period where the device does not respond to changes on WDI. After this 150-μs period, the

device begins to respond to changes on WDI again.

SET0

SET1

VDD1 = VDD2

RATIO

Disabled

1:8

1:8

tWD-setup

Figure 7-2. Enabling the Watchdog Timer

7.3.2.1.2 Disabling the Watchdog Timer When Using the CRST Capacitor

When using the TPS3430 with fixed timing options, if the watchdog is disabled and reenabled while WDO is

asserted (logic low) the watchdog performs as described in the Section 7.3.2.1.1 section. However, if there is

a capacitor on the CRST pin, and the watchdog is disabled and reenabled when WDO is asserted (logic low),

then the watchdog behaves as shown in Figure 7-3. When the watchdog is disabled, WDO goes high impedance

(logic high). However, when the watchdog is enabled again, the tRST period must expire before the watchdog

resumes normal operation.

SET1

VDD1 = VDD2

SET0

WDO

Disabling and

Enabling

watchdog

tRST

tWDU

tWDU

There is no WDI signal in this figure, WDI is always at GND.

Figure 7-3. Enabling and Disabling the Watchdog Timer During a WDO Reset Event

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TPS3430

SBVS366A – JULY 2018 – REVISED OCTOBER 2021

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Product Folder Links: TPS3430