C8051F310 datasheet(108/228 Pages) SILABS

108 / 228 page

C8051F310/1/2/3/4/5/6/7

108

Rev. 1.7

9.4.

Missing Clock Detector Reset

The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system

clock remains high or low for more than 100 µs, the one-shot will time out and generate a reset. After a

MCD reset, the MCDRSF flag (RSTSRC.2) will read ‘1’, signifying the MCD as the reset source; otherwise,

this bit reads ‘0’. Writing a ‘1’ to the MCDRSF bit enables the Missing Clock Detector; writing a ‘0’ disables

it. The state of the RST pin is unaffected by this reset.

9.5.

Comparator0 Reset

Comparator0 can be configured as a reset source by writing a ‘1’ to the C0RSEF flag (RSTSRC.5).

Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on

chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-

inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into

the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read ‘1’ signifying

Comparator0 as the reset source; otherwise, this bit reads ‘0’. The state of the RST pin is unaffected by

this reset.

9.6.

PCA Watchdog Timer Reset

The programmable Watchdog Timer (WDT) function of the Programmable Counter Array (PCA) can be

used to prevent software from running out of control during a system malfunction. The PCA WDT function

can be enabled or disabled by software as described in Section “18.3. Watchdog Timer Mode” on

page 212; the WDT is enabled and clocked by SYSCLK / 12 following any reset. If a system malfunction

prevents user software from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is

set to ‘1’. The state of the RST pin is unaffected by this reset.

9.7.

Flash Error Reset

If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This

may occur due to any of the following:

•

A Flash write or erase is attempted above user code space. This occurs when PSWE is set to ‘1’ and a

MOVX write operation targets an address above address 0x3DFF for C8051F310/1 or 0x1FFF for

C8051F312/3/4/5.

•

A Flash read is attempted above user code space. This occurs when a MOVC operation targets an

address above address 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5.

•

A Program read is attempted above user code space. This occurs when user code attempts to branch

to an address above 0x3DFF for C8051F310/1 or 0x1FFF for C8051F312/3/4/5.

•

A Flash read, write or erase attempt is restricted due to a Flash security setting (see Section

“10.3. Security Options” on page 113).

The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by

this reset.

9.8.

Software Reset

Software may force a reset by writing a ‘1’ to the SWRSF bit (RSTSRC.4). The SWRSF bit will read ‘1’ fol-

lowing a software forced reset. The state of the RST pin is unaffected by this reset.

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