C8051F310 datasheet(132/228 Pages) SILABS

132 / 228 page

C8051F310/1/2/3/4/5/6/7

132

Rev. 1.7

Figure 13.4. Crossbar Priority Decoder with Crystal Pins Skipped

Registers XBR0 and XBR1 are used to assign the digital I/O resources to the physical I/O Port pins. Note

that when the SMBus is selected, the Crossbar assigns both pins associated with the SMBus (SDA and

SCL); when the UART is selected, the Crossbar assigns both pins associated with the UART (TX and RX).

UART0 pin assignments are fixed for bootloading purposes: UART TX0 is always assigned to P0.4; UART

RX0 is always assigned to P0.5. Standard Port I/Os appear contiguously after the prioritized functions

have been assigned.

Important Note: The SPI can be operated in either 3-wire or 4-wire modes, pending the state of the

NSSMD1-NSSMD0 bits in register SPI0CN. According to the SPI mode, the NSS signal may or may not be

routed to a Port pin.

2345670

123456

7012345

SCK

MISO

MOSI

NSS*

CP0

CP0A

CP1

1100000

000000

00000

CEX2

CEX0

CEX1

SYSCLK

CP1A

CEX3

CEX4

SF Signals

PIN I/O

TX0

RX0

SDA

SCL

Special Function Signals are not assigned by the Crossbar. When these signals are enabled, the Crossbar must

be manually configured to skip their corresponding port pins.

Port pin potentially available to peripheral

SF Signals

ECI

P0SKIP[0:7]

P2SKIP[0:3]

P1SKIP[0:7]

*Note:

NSS is only pinned out in 4-wire SPI mode.

Note:

P1.6,P1.7,P2.6,P2.7 only available on the C8051F310/1/2/3/4/5; P1SKIP[7:6] should always be set to

11b for the C8051F316/7 devices.

C8051F310 Datasheet(PDF) 132 Page - Silicon Laboratories

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