C8051F310 datasheet(134/228 Pages) SILABS

134 / 228 page

C8051F310/1/2/3/4/5/6/7

134

Rev. 1.7

SFR Definition 13.1. XBR0: Port I/O Crossbar Register 0

Bit7:

CP1AE: Comparator1 Asynchronous Output Enable

0: Asynchronous CP1 unavailable at Port pin.

1: Asynchronous CP1 routed to Port pin.

Bit6:

CP1E: Comparator1 Output Enable

0: CP1 unavailable at Port pin.

1: CP1 routed to Port pin.

Bit5:

CP0AE: Comparator0 Asynchronous Output Enable

0: Asynchronous CP0 unavailable at Port pin.

1: Asynchronous CP0 routed to Port pin.

Bit4:

CP0E: Comparator0 Output Enable

0: CP0 unavailable at Port pin.

1: CP0 routed to Port pin.

Bit3:

SYSCKE: /SYSCLK Output Enable

0: /SYSCLK unavailable at Port pin.

1: /SYSCLK output routed to Port pin.

Bit2:

SMB0E: SMBus I/O Enable

0: SMBus I/O unavailable at Port pins.

1: SMBus I/O routed to Port pins.

Bit1:

SPI0E: SPI I/O Enable

0: SPI I/O unavailable at Port pins.

1: SPI I/O routed to Port pins.

Bit0:

URT0E: UART I/O Output Enable

0: UART I/O unavailable at Port pin.

1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.

R/W

Reset Value

CP1AE

CP1E

CP0AE

CP0E

SYSCKE

SMB0E

SPI0E

URT0E

00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE1

C8051F310 Datasheet(PDF) 134 Page - Silicon Laboratories

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