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C8051F310 Datasheet(PDF) 137 Page - Silicon Laboratories |
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C8051F310 Datasheet(HTML) 137 Page - Silicon Laboratories |
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137 / 228 page ![]() Rev. 1.7 137 C8051F310/1/2/3/4/5/6/7 SFR Definition 13.5. P0MDOUT: Port0 Output Mode SFR Definition 13.6. P0SKIP: Port0 Skip Bits7–0: Output Configuration Bits for P0.7–P0.0 (respectively): ignored if corresponding bit in regis- ter P0MDIN is logic 0. 0: Corresponding P0.n Output is open-drain. 1: Corresponding P0.n Output is push-pull. Note: When SDA and SCL appear on any of the Port I/O, each are open-drain regardless of the value of P0MDOUT. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xA4 Bits7–0: P0SKIP[7:0]: Port0 Crossbar Skip Enable Bits. These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana- log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil- lator circuit, CNVSTR input) should be skipped by the Crossbar. 0: Corresponding P0.n pin is not skipped by the Crossbar. 1: Corresponding P0.n pin is skipped by the Crossbar. R/W R/W R/W R/W R/W R/W R/W R/W Reset Value 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address: 0xD4 |
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