21152 datasheet(67/148 Pages) INTEL

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21152 PCI-to-PCI Bridge Preliminary Datasheet

5-5

Address Decoding

base and limit address registers, and VGA mode bit before setting the memory enable and master

enable bits, and change them subsequently only when the primary and secondary PCI buses are idle.

5.3.1

Memory-Mapped I/O Base and Limit Address Registers

Memory-mapped I/O is also referred to as nonprefetchable memory. Memory addresses that cannot

automatically be prefetched but that can conditionally prefetch based on command type should be

mapped into this space. Read transactions to nonprefetchable space may exhibit side effects; this

space may have non-memory-like behavior. The 21152 prefetches in this space only if the memory

read line or memory read multiple commands are used; transactions using the memory read

command are limited to a single data transfer.

The memory-mapped I/O base address and memory-mapped I/O limit address registers define an

address range that the 21152 uses to determine when to forward memory commands. The 21152

forwards a memory transaction from the primary to the secondary interface if the transaction

address falls within the memory-mapped I/O address range. The 21152 ignores memory

transactions initiated on the secondary interface that fall into this address range. Any transactions

that fall outside this address range are ignored on the primary interface and are forwarded upstream

from the secondary interface (provided that they do not fall into the prefetchable memory range or

are not forwarded downstream by the VGA mechanism).

The memory-mapped I/O range supports 32-bit addressing only. The PCI-to-PCI Bridge

Architecture Specification does not provide for 64-bit addressing in the memory-mapped I/O space.

The memory-mapped I/O address range has a granularity and alignment of 1 MB. The maximum

memory-mapped I/O address range is 4 GB.

The memory-mapped I/O address range is defined by a 16-bit memory-mapped I/O base address

offset 22h. The top 12 bits of each of these registers correspond to bits <31:20> of the memory

address. The low 4 bits are hardwired to 0. The low 20 bits of the memory-mapped I/O base

address are assumed to be 0 0000h, which results in a natural alignment to a 1MB boundary. The

low 20 bits of the memory-mapped I/O limit address are assumed to be F FFFFh, which results in

an alignment to the top of a 1MB block.

Note:

The initial state of the memory-mapped I/O base address register is 0000 0000h. The initial state of

the memory-mapped I/O limit address register is 000F FFFFh. Note that the initial states of these

registers define a memory-mapped I/O range at the bottom 1MB block of memory. Write these

registers with their appropriate values before setting either the memory enable bit or the master

enable bit in the command register in configuration space.

To turn off the memory-mapped I/O address range, write the memory-mapped I/O base address

21152 Datasheet(PDF) 67 Page - Intel Corporation