21152 datasheet(22/148 Pages) INTEL

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2-6

21152 PCI-to-PCI Bridge Preliminary Datasheet

Signal Pins

s_devsel_l

STS

Secondary PCI interface DEVSEL#. Signal s_devsel_l is asserted by the

target, indicating that the device is accepting the transaction. As a target, the

21152 performs positive decoding on the address of a transaction initiated on the

secondary bus in order to determine whether to assert s_devsel_l. As an initiator

of a transaction on the secondary bus, the 21152 looks for the assertion of

s_devsel_l within five cycles of s_frame_l assertion; otherwise, the 21152

terminates the transaction with a master abort. When the secondary bus is idle,

s_devsel_l is driven to a deasserted state for one cycle and then is sustained by

an external pull-up resistor.

s_stop_l

STS

Secondary PCI interface STOP#. Signal s_stop_l is driven by the target of the

current transaction, indicating that the target is requesting the initiator to stop the

current transaction on the secondary bus.

•

When s_stop_l is asserted in conjunction with s_trdy_l and s_devsel_l

assertion, a disconnect with data transfer is being signaled.

•

When s_stop_l and s_devsel_l are asserted, but s_trdy_l is deasserted, a

target disconnect without data transfer is being signaled. When this occurs

on the first data phase, that is, no data is transferred during the transaction,

this is referred to as a target retry.

•

When s_stop_l is asserted and s_devsel_l is deasserted, the target is

signaling a target abort.

When the secondary bus is idle, s_stop_l is driven to a deasserted state for one

cycle and then is sustained by an external pull-up resistor.

s_lock_l

STS

Secondary PCI interface LOCK#. Signal s_lock_l is deasserted during the first

address phase of a transaction and is asserted one clock cycle later by the 21152

when it is propagating a locked transaction downstream. The 21152 does not

propagate locked transactions upstream. The 21152 continues to assert s_lock_l

until the address phase of the next locked transaction, or until the lock is

released. When the lock is released, s_lock_l is driven to a deasserted state for

one cycle and then is sustained by an external pull-up resistor.

s_perr_l

STS

Secondary PCI interface PERR#. Signal s_perr_l is asserted when a data

parity error is detected for data received on the secondary interface. The timing of

s_perr_l corresponds to s_par driven one cycle earlier and s_ad driven two

cycles earlier. Signal s_perr_l is asserted by the target during write transactions,

and by the initiator during read transactions. When the secondary bus is idle,

s_perr_l is driven to a deasserted state for one cycle and then is sustained by an

external pull-up resistor.

s_serr_l

Secondary PCI interface SERR#. Signal s_serr_l can be driven low by any

device except the 21152 on the secondary bus to indicate a system error

condition. The 21152 samples s_serr_l as an input and conditionally forwards it

to the primary bus on p_serr_l. The 21152 does not drive s_serr_l. Signal

s_serr_l is pulled up through an external resistor.

Table 2-4.

Secondary PCI Bus Interface Signals (Sheet 2 of 2)

Signal Name

Type

Description

21152 Datasheet(PDF) 22 Page - Intel Corporation

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