21152 datasheet(69/148 Pages) INTEL

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21152 PCI-to-PCI Bridge Preliminary Datasheet

5-7

Address Decoding

5.3.2

Prefetchable Memory Base and Limit Address Registers

Locations accessed in the prefetchable memory address range must have true memory-like

behavior and must not exhibit side effects when read. This means that extra reads to a prefetchable

memory location must have no side effects. The 21152 prefetches for all types of memory read

commands in this address space.

The prefetchable memory base address and prefetchable memory limit address registers define an

address range that the 21152 uses to determine when to forward memory commands. The 21152

forwards a memory transaction from the primary to the secondary interface if the transaction

address falls within the prefetchable memory address range. The 21152 ignores memory

transactions initiated on the secondary interface that fall into this address range. The 21152 does

not respond to any transactions that fall outside this address range on the primary interface and

forwards those transactions upstream from the secondary interface (provided that they do not fall

into the memory-mapped I/O range or are not forwarded by the VGA mechanism).

The prefetchable memory range supports 64-bit addressing and provides additional registers to

define the upper 32 bits of the memory address range, the prefetchable memory base address upper

32 bits register, and the prefetchable memory limit address upper 32 bits register. For address

comparison, a single address cycle (32-bit address) prefetchable memory transaction is treated like

a 64-bit address transaction where the upper 32 bits of the address are equal to 0. This upper 32-bit

value of 0 is compared to the prefetchable memory base address upper 32 bits register and the

prefetchable memory limit address upper 32 bits register. The prefetchable memory base address

upper 32 bits register must be 0 in order to pass any single address cycle transactions downstream.

Section 5.3.3 further describes 64-bit addressing support.

The prefetchable memory address range has a granularity and alignment of 1 MB. The maximum

memory address range is 4 GB when 32-bit addressing is used, and 2

24 bytes when 64-bit

addressing is used.

The prefetchable memory address range is defined by a 16-bit prefetchable memory base address

offset 28h. The top 12 bits of each of these registers correspond to bits <31:20> of the memory

address. The low 4 bits are hardwired to 1h, indicating 64-bit address support. The low 20 bits of

the prefetchable memory base address are assumed to be 0 0000h, which results in a natural

alignment to a 1 MB boundary. The low 20 bits of the prefetchable memory limit address are

assumed to be F FFFFh, which results in an alignment to the top of a 1 MB block.

Note:

The initial state of the prefetchable memory base address register is 0000 0000h. The initial state of

the prefetchable memory limit address register is 000F FFFFh. Note that the initial states of these

registers define a prefetchable memory range at the bottom 1 MB block of memory. Write these

registers with their appropriate values before setting either the memory enable bit or the master

enable bit in the command register in configuration space.

To turn off the prefetchable memory address range, write the prefetchable memory base address

base value must be greater than the entire limit value, meaning that the upper 32 bits must be

considered. Therefore, to disable the address range, the upper 32 bits registers can both be set to the

same value, while the lower base register is set greater than the lower limit register; otherwise, the

upper 32-bit base must be greater than the upper 32-bit limit.

21152 Datasheet(PDF) 69 Page - Intel Corporation

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