21152 datasheet(21/148 Pages) INTEL

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21152 PCI-to-PCI Bridge Preliminary Datasheet

2-5

Signal Pins

2.2

Secondary PCI Bus Interface Signals

Table 2-4 describes the secondary PCI bus interface signals.

Table 2-4.

Secondary PCI Bus Interface Signals (Sheet 1 of 2)

Signal Name

Type

Description

s_ad<31:0>

Secondary PCI interface address/data. These signals are a multiplexed

address and data bus. During the address phase or phases of a transaction, the

initiator drives a physical address on s_ad<31:0>. During the data phases of a

transaction, the initiator drives write data, or the target drives read data, on

s_ad<31:0>. When the secondary PCI bus is idle, the 21152 drives s_ad to a

valid logic level when its secondary bus grant is asserted.

s_cbe_l<3:0>

Secondary PCI interface command/byte enables. These signals are a

multiplexed command field and byte enable field. During the address phase or

phases of a transaction, the initiator drives the transaction type on s_cbe_l<3:0>.

When there are two address phases, the first address phase carries the dual

address command and the second address phase carries the transaction type. For

both read and write transactions, the initiator drives byte enables on s_cbe_l<3:0>

during the data phases. When the secondary PCI bus is idle, the 21152 drives

s_cbe_l to a valid logic level when its secondary bus grant is asserted.

s_par

Secondary PCI interface parity. Signal s_par carries the even parity of the 36

bits of s_ad<31:0> and s_cbe_l<3:0> for both address and data phases. Signal

s_par is driven by the same agent that has driven the address (for address

parity) or the data (for data parity). Signal s_par contains valid parity one cycle

after the address is valid (indicated by assertion of s_frame_l), or one cycle after

data is valid (indicated by assertion of s_irdy_l for write transactions and

s_trdy_l for read transactions). Signal s_par is driven by the device driving read

or write data one cycle after s_ad is driven. Signal s_par is tristated one cycle

after the s_ad lines are tristated. Devices receive data sample s_par as an input

to check for possible parity errors. When the secondary PCI bus is idle, the 21152

drives s_par to a valid logic level when its secondary bus grant is asserted (one

cycle after the s_ad bus is parked).

s_frame_l

STS

Secondary PCI interface FRAME#. Signal s_frame_l is driven by the initiator of

a transaction to indicate the beginning and duration of an access on the

secondary PCI bus. Signal s_frame_l assertion (falling edge) indicates the

beginning of a PCI transaction. While s_frame_l remains asserted, data transfers

can continue. The deassertion of s_frame_l indicates the final data phase

requested by the initiator. When the secondary PCI bus is idle, s_frame_l is

driven to a deasserted state for one cycle and then is sustained by an external

pull-up resistor.

s_irdy_l

STS

Secondary PCI interface IRDY#. Signal s_irdy_l is driven by the initiator of a

transaction to indicate the initiator’s ability to complete the current data phase on

the secondary PCI bus. During a write transaction, assertion of s_irdy_l indicates

that valid write data is being driven on the s_ad bus. During a read transaction,

assertion of s_irdy_l indicates that the initiator is able to accept read data for the

current data phase. Once asserted during a given data phase, s_irdy_l is not

deasserted until the data phase completes. When the secondary bus is idle,

s_irdy_l is driven to a deasserted state for one cycle and then is sustained by an

external pull-up resistor.

s_trdy_l

STS

Secondary PCI interface TRDY#. Signal s_trdy_l is driven by the target of a

transaction to indicate the target’s ability to complete the current data phase on

the secondary PCI bus. During a write transaction, assertion of s_trdy_l indicates

that the target is able to accept write data for the current data phase. During a

read transaction, assertion of s_trdy_l indicates that the target is driving valid

read data on the s_ad bus. Once asserted during a given data phase, s_trdy_l is

not deasserted until the data phase completes. When the secondary bus is idle,

s_trdy_l is driven to a deasserted state for one cycle and then is sustained by an

external pull-up resistor.

21152 Datasheet(PDF) 21 Page - Intel Corporation

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