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21152 Datasheet(PDF) 64 Page - Intel Corporation |
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21152 Datasheet(HTML) 64 Page - Intel Corporation |
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64 / 148 page ![]() 5-2 21152 PCI-to-PCI Bridge Preliminary Datasheet Address Decoding 5.2.1 I/O Base and Limit Address Registers The 21152 implements one set of I/O base and limit address registers in configuration space that define an I/O address range for downstream forwarding. The 21152 supports 32-bit I/O addressing, which allows I/O addresses downstream of the 21152 to be mapped anywhere in a 4 GB I/O address space. I/O transactions with addresses that fall inside the range defined by the I/O base and limit registers are forwarded downstream from the primary PCI bus to the secondary PCI bus. I/O transactions with addresses that fall outside this range are forwarded upstream from the secondary PCI bus to the primary PCI bus. The I/O range can be turned off by setting the I/O base address to a value greater than that of the I/O limit address. When the I/O range is turned off, all I/O transactions are forwarded upstream, and no I/O transactions are forwarded downstream. Figure 5-1 illustrates transaction forwarding within and outside the I/O address range. The 21152 I/O range has a minimum granularity of 4 KB and is aligned on a 4 KB boundary. The maximum I/O range is 4 GB in size. The I/O base register consists of an 8-bit field at configuration address 1Ch, and a 16-bit field at address 30h. The top 4 bits of the 8-bit field define bits <15:12> of the I/O base address. The bottom 4 bits read only as 1h to indicate that the 21152 supports 32-bit I/O addressing. Bits <11:0> of the base address are assumed to be 0, which naturally aligns the base address to a 4 KB boundary. The 16 bits contained in the I/O base upper 16 bits register at configuration offset 30h define AD<31:16> of the I/O base address. All 16 bits are read/write. After primary bus reset or chip reset, the value of the I/O base address is initialized to 0000 0000h. Figure 5-1. I/O Transaction Forwarding Using Base and Limit Addresses LJ-04636.AI4 I/O Limit Primary Interface Secondary Interface 4KB Multiple I/O Base I/O Address Space |
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