21152 datasheet(47/148 Pages) INTEL

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21152 PCI-to-PCI Bridge Preliminary Datasheet

4-13

PCI Bus Operation

4.6.4

Delayed Read Requests

The 21152 treats all read transactions as delayed read transactions, which means that the read

request from the initiator is posted into a delayed transaction queue. Read data from the target is

placed in the read data queue directed toward the initiator bus interface and is transferred to the

initiator when the initiator repeats the read transaction.

When the 21152 accepts a delayed read request, it first samples the read address, read bus

command, and address parity. When IRDY# is asserted, the 21152 then samples the byte enable

bits for the first data phase. This information is entered into the delayed transaction queue. The

21152 terminates the transaction by signaling a target retry to the initiator. Upon reception of the

target retry, the initiator is required to continue to repeat the same read transaction until at least one

data transfer is completed, or until a target response other than a target retry (target abort, or master

abort) is received.

4.6.5

Delayed Read Completion with Target

When the delayed read request reaches the head of the delayed transaction queue, and all

previously queued posted write transactions have been delivered, the 21152 arbitrates for the target

bus and initiates the read transaction, using the exact read address and read command captured

from the initiator during the initial delayed read request. If the read transaction is a nonprefetchable

read, the 21152 drives the captured byte enable bits during the next cycle. If the transaction is a

prefetchable read transaction, it drives all byte enable bits to 0 for all data phases. If the 21152

receives a target retry in response to the read transaction on the target bus, it continues to repeat the

read transaction until at least one data transfer is completed, or until an error condition is

encountered. If the transaction is terminated via normal master termination or target disconnect

after at least one data transfer has been completed, the 21152 does not initiate any further attempts

to read more data.

If the 21152 is unable to obtain read data from the target after 224 attempts, the 21152 ceases

further read attempts and returns a target abort to the initiator. The delayed transaction is removed

from the delayed transaction queue. The 21152 also asserts p_serr_l if the primary SERR# enable

bit is set in the command register. See Section 7.4 for information on the assertion of p_serr_l.

Once the 21152 receives DEVSEL# and TRDY# from the target, it transfers the data read to the

opposite direction read data queue, pointing toward the opposite interface, before terminating the

transaction. For example, read data in response to a downstream read transaction initiated on the

primary bus is placed in the upstream read data queue. The 21152 can accept 1 Dword of read data

each PCI clock cycle; that is, no master wait states are inserted. The number of Dwords transferred

during a delayed read transaction depends on the conditions given in Table 4.5 (assuming no

disconnect is received from the target).

21152 Datasheet(PDF) 47 Page - Intel Corporation