21152 datasheet(52/148 Pages) INTEL

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21152 PCI-to-PCI Bridge Preliminary Datasheet

PCI Bus Operation

4.7.1

Type 0 Access to the 21152

The 21152 configuration space is accessed by a Type 0 configuration transaction on the primary

interface. The 21152 configuration space cannot be accessed from the secondary bus. The 21152

responds to a Type 0 configuration transaction by asserting p_devsel_l when the following

conditions are met during the address phase:

• The bus command is a configuration read or configuration write transaction.

• Low 2 address bits p_ad<1:0> must be 00b.

• Signal p_idsel must be asserted.

The function code is ignored because the 21152 is a single-function device.

The 21152 limits all configuration accesses to a single Dword data transfer and returns a target

disconnect with the first data transfer if additional data phases are requested. Because read

transactions to 21152 configuration space do not have side effects, all bytes in the requested Dword

are returned, regardless of the value of the byte enable bits.

Type 0 configuration write and read transactions do not use 21152 data buffers; that is, these

transactions are completed immediately, regardless of the state of the data buffers.

The 21152 ignores all Type 0 transactions initiated on the secondary interface.

4.7.2

Type 1 to Type 0 Translation

Type 1 configuration transactions are used specifically for device configuration in a hierarchical PCI bus

system. A PCI-to-PCI bridge is the only type of device that should respond to a Type 1 configuration

command. Type 1 configuration commands are used when configuration access is intended for a PCI

device residing on a PCI bus other than the one where the Type 1 transaction is generated.

The 21152 performs a Type 1 to Type 0 translation when the Type 1 transaction is generated on the

primary bus and is intended for a device attached directly to the secondary bus. The 21152 must

convert the configuration command to a Type 0 format so that the secondary bus device can

respond to it. Type 1 to Type 0 translations are performed only in the downstream direction; that is,

the 21152 generates a Type 0 transaction only on the secondary bus, and never on the primary bus.

The 21152 responds to a Type 1 configuration transaction and translates it into a Type 0 transaction

on the secondary bus when the following conditions are met during the address phase:

• The low 2 address bits on p_ad<1:0> are 01b.

• The bus number in address field p_ad<23:16> is equal to the value in the secondary bus

number register in 21152 configuration space.

• The bus command on p_cbe_l<3:0> is a configuration read or configuration write transaction.

When the 21152 translates the Type 1 transaction to a Type 0 transaction on the secondary

interface, it performs the following translations to the address:

• Sets the low 2 address bits on s_ad<10> to 00b

• Decodes the device number and drives the bit pattern specified in Table 4.6 on s_ad<31:16>

for the purpose of asserting the device’s IDSEL signal

• Sets s_ad<15:11> to 0

• Leaves unchanged the function number and register number fields

21152 Datasheet(PDF) 52 Page - Intel Corporation

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