IMX27L datasheet(81/122 Pages) FREESCALE

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Signal Descriptions

i.MX27/i.MX27L Data Sheet, Advance Information, Rev. 1

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

Figure 41. Mobile DDR SDRAM Write Cycle Timing Diagram

NOTE

SDRAM CLK and DQS related parameters are being measured from the

50% point—that is, high is defined as 50% of signal value and low is

defined as 50% of signal value.

The timing parameters are similar to the ones used in SDRAM data

sheets—that is, Table 40 indicates SDRAM requirements. All output signals

are driven by the ESDCTL at the negative edge of SDCLK and the

parameters are measured at maximum memory frequency.

Table 40. Mobile DDR SDRAM Write Cycle Timing Parameters1

1 Test condition: Measured using delay line 5 programmed as follows: ESDCDLY5[15:0] = 0x0703.

Parameter

Symbol

Min

Max

Unit

SD17

DQ and DQM setup time to DQS

tDS

0.95

—

SD18

DQ and DQM hold time to DQS

tDH

0.95

—

SD19

Write cycle DQS falling edge to SDCLK output delay time.

tDSS

1.8

—

SD20

Write cycle DQS falling edge to SDCLK output hold time.

tDSH

1.8

—

SDCLK

DQS (output)

DQ (output)

DQM (output)

Data

SD17

SD18

SD19

SD20

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