IMX27L datasheet(94/122 Pages) FREESCALE

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i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Signal Descriptions

NOTE

All the timings for the SSI are given for a non-inverted serial clock polarity

(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the

polarity of the clock and/or the frame sync have been inverted, all the timing

remains valid by inverting the clock signal STCK/SRCK and/or the frame

sync STFS/SRFS shown in the tables and in the figures.

All timings are on AUDMUX pads when the SSI is being used for data

transfer.

“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.

For internal frame sync operation using external clock, the FS timing is the

same as that of Tx Data, for example, during the AC97 mode of operation.

3.6.12

Wireless External Interface Module (WEIM)

All WEIM output control signals may be asserted and deasserted by internal clock related to BCLK rising

edge or falling edge according to corresponding assertion/negation control fields. Address always begins

related to BCLK falling edge but may be ended both on rising and falling edge in muxed mode according

to control register configuration. Output data begins related to BCLK rising edge except in muxed mode

where both rising and falling edge may be used according to control register configuration. Input data,

ECB and DTACK all captured according to BCLK rising edge time. Figure 53 shows the timing of the

WEIM module, and Table 49 lists the timing parameters.

SS24

(Tx/Rx) CK clock rise time

—

6.0

SS25

(Tx/Rx) CK clock low period

36.0

—

SS26

(Tx/Rx) CK clock fall time

—

6.0

SS28

(Rx) CK high to FS (bl) high

–10.0

15.0

SS30

(Rx) CK high to FS (bl) low

10.0

—

SS32

(Rx) CK high to FS (wl) high

–10.0

15.0

SS34

(Rx) CK high to FS (wl) low

10.0

—

SS35

(Tx/Rx) External FS rise time

—

6.0

SS36

(Tx/Rx) External FS fall time

—

6.0

SS40

SRXD setup time before (Rx) CK low

10.0

—

SS41

SRXD hold time after (Rx) CK low

2.0

—

Table 48. SSI Receiver with External Clock Timing Parameters (continued)

Parameter

Min

Max

Unit

IMX27L Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc

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