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IMX27L Datasheet(PDF) 92 Page - Freescale Semiconductor, Inc |
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IMX27L Datasheet(HTML) 92 Page - Freescale Semiconductor, Inc |
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92 / 122 page ![]() i.MX27/iMX27L Data Sheet, Advance Information, Rev. 1 92 Preliminary—Subject to Change Without Notice Freescale Semiconductor Signal Descriptions NOTE All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures. All timings are on AUDMUX pads when the SSI is being used for data transfer. “Tx” and “Rx” refer to the Transmit and Receive sections of the SSI. For internal frame sync operation using external clock, the FS timing is the same as that of Tx Data, for example, during the AC97 mode of operation. Table 47. SSI Transmitter with External Clock Timing Parameters ID Parameter Min Max Unit External Clock Operation SS22 (Tx/Rx) CK clock period 81.4 — ns SS23 (Tx/Rx) CK clock high period 36.0 — ns SS24 (Tx/Rx) CK clock rise time — 6.0 ns SS25 (Tx/Rx) CK clock low period 36.0 — ns SS26 (Tx/Rx) CK clock fall time — 6.0 ns SS27 (Tx) CK high to FS (bl) high –10.0 15.0 ns SS29 (Tx) CK high to FS (bl) low 10.0 — ns SS31 (Tx) CK high to FS (wl) high –10.0 15.0 ns SS33 (Tx) CK high to FS (wl) low 10.0 — ns SS37 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS38 (Tx) CK high to STXD high/low — 15.0 ns SS39 (Tx) CK high to STXD high impedance — 15.0 ns Synchronous External Clock Operation SS44 SRXD setup before (Tx) CK falling 10.0 — ns SS45 SRXD hold after (Tx) CK falling 2.0 — ns SS46 SRXD rise/fall time — 6.0 ns |
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